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Split-path data driven dynamic logic (SPD3L) is used wherever low power design is desired. It uses subset of input signals instead of global clock to maintain the correct pre-charge and evaluation phases. Elimination of clock network results in substantial reduction in power dissipation compared to dynamic domino logic. In this work, two 6×6 booth multipliers are implemented in 1.8V 0.18um CMOS technology,...
Two symmetrically corrugated diaphragms are bonded to form a capsule of special structure and this is used for sensing displacement caused by applied pressure. The displacement is converted into equivalent capacitance by optimally fixed stack of plates and an electrical signal is picked up from it proportional to capacitance. This signal picked up is then calibrated for pressure acting on the capsules...
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