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Split-path data driven dynamic logic (SPD3L) is used wherever low power design is desired. It uses subset of input signals instead of global clock to maintain the correct pre-charge and evaluation phases. Elimination of clock network results in substantial reduction in power dissipation compared to dynamic domino logic. In this work, two 6×6 booth multipliers are implemented in 1.8V 0.18um CMOS technology,...
Clock Distribution has played a key role in designing the synchronous systems. Even with the systems moving towards Globally Asynchronous and Locally Synchronous (GALS) a need for low power clock distribution network exists as it consumes a major portion of the circuit power. In this paper we demonstrate the effect of various level converters on clock distribution networks. Also we propose a novel...
PWLL, the p-Wave Locked Loop, helps determining instantaneously the p to p time interval of the ECG and enables us to perform heart rate variability studies with p_p variation. In the previous PWLL circuit, the prefixed delay given for changing over from r-wave to p-wave might fail to work for certain abnormal p_p variations present in ECGs. In this improved version of the PWLL, the time duration...
A multi-lingual TV system needs to broadcast the video with audio appearing in more than one language. In the receiver it gives option to the viewer to choose the desired language for his audio. This paper reports the realization of a TV channel incorporating six audio tracks needed for transmitting three stereo sounds. Four tracks of the audio are adaptive delta modulated and inserted in the Hsync...
This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction...
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