The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Since D flip-flop is one of the indispensable building blocks in integrated circuit (IC) design, providing a successful way to print D flip-flop on plastic foils will be the first step to reach fully printed flexible IC. Here, the network structure of single-walled carbon nanotubes (SWNTs) as an active layer has been employed to print the driver and load thin-film transistors (TFTs) of the D flip-flop...
This paper discusses a grid-type sensor network with reconfigurable PSoCs as sensor nodes, and details the middleware routines that support the high-level model for distributed programming. The advantages of using reconfigurable PSoCs over other architectures, like MICA2 motes, are also discussed. The paper refers to a case study to illustrate the capabilities of the proposed network concept.
Physical and environmental variations require the addition of safety margins to the clock frequency of digital systems, making it overly conservative. Aggressive, but reliable, dynamic clock frequency tuning mechanisms that achieve higher system performance, by adapting the clock rates beyond worst case limits, have been proposed earlier. Even though reliable over-clocking guarantees functional correctness,...
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely soft error mitigation (SEM) and soft and timing error mitigation (STEM), for protecting combinational logic blocks from soft errors. Our first technique (SEM), based on distributed and...
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree of fault tolerance and enhances performance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.