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In this paper, the skin effect of on-chip transmission lines and inductors at K-Band operating frequencies are investigated. Two microstrip lines with different lengths are simulated and compared with each other. A patterned ground shielded inductor is simulated using various meshing strategies and the results are compared. A 24 GHz common source CMOS low noise amplifier is designed, simulated and...
A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 μm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a small-signal power gain of 16.2 dB, a maximum...
A fully integrated CMOS receiver consisting of an LNA and a mixer has been designed and fabricated in IBM BiCMOS 7WL 180 nm technology. An on-chip balun loading the second stage of the LNA was implemented as well for single-to-differential conversion. The receiver was developed for high performance wireless local positioning systems and excellent experimental results were demonstrated: a conversion...
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached...
A digitally controlled variable gain amplifier (VGA) for low power, low-IF receivers is presented. The amplifier was designed and fabricated in IBM 7WL BiCMOS 180 nm technology. It shows a dynamic range of 45 dB with a maximum gain of 52 dB and a minimum gain of 7 dB. The gain variation is achieved by means of switched feedback resistors. These are controlled by a demultiplexer and 4 control bits...
Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of-3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported...
New process modules and device architectures for (sub-) 32 nm CMOS lead to both opportunities and challenges for analog/RF and mm-wave circuit design. A survey will be given describing the advanced process modules and competing architectures (planar bulk CMOS versus FinFETS), and their impact on analog/RF performance. FinFETs will be shown to be better suited for analog baseband design and to have...
There has been significant interest in the applications of printed electronics in the realization of fully-printed RFID tags and embedded sensors. Printing of active circuitry is expected to enable a dramatic reduction in the overall cost of these systems, allowing for integration of electronic barcodes and product quality detection systems into consumer goods. In this talk, I will review our work...
A folded double-balanced mixer has been implemented in a 0.18 mum BiCMOS technology for wireless local positioning applications. Operating in the unlicensed ISM band centred at 5.8 GHz with a 150 MHz bandwidth and with a very low IF frequency band from 500 kHz up to 5 MHz, the mixer achieves 17 dB voltage conversion gain, 8.5 dB noise figure and input IP3 of - 6 dBm. The mixer power consumption is...
Target of this work is to explain the significance of electromagnetic effects due to on-chip spiral inductors and passive interconnects on the circuit behavior. Starting from the design aspects of spiral inductors in a cascode CMOS LNA, the influence of their on-chip coupling on the reverse isolation performance of the amplifier will be presented. The importance of the careful consideration of on-chip...
This work demonstrates the design of a wideband low noise amplifier in 0.13 um CMOS technology. Important design aspects and the influence of bandwidth improving circuit elements on various LNA performance parameters like gain, matching, noise figure, and stability are analyzed. Simulated and measured LNA results are presented. At the centre frequency of 5.5 GHz the measured LNA performance includes...
CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount...
This work presents a fully integrated 6 GHz LNA designed using 0.12 mum IBM CMOS technology. The amplifier consumes only 3.6 mW dc power with 1.2 V supply voltage, and features a 11 dB power gain and 3.6 dB noise figure at the frequency of 6 GHz. Additionally, it achieves -11 dBm of input referred 1 dB compression point and -0.5 dBm of IIP3. At the same time input and output matching are better than...
Wireless applications require a low power technology that enables digital/analog/RF functions on the same chip. FinFET technology presents a competitive alternative to planar CMOS as it features good digital, analog and low-frequency noise performances. Also, very good matching performance is presented here for the first time. Moreover, FinFETs are shown to be attractive for low-power applications...
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