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This paper presents a low cost implementation of the phase-based sound localization method proposed in Halupka et al [2]. The implementation uses PSoC programmable mixed-signal embedded System on Chip, which incorporates microcontroller, on-chip SRAM and flash memory, programmable digital blocks and programmable analog blocks, all integrated on the same chip. In order to improve the localization accuracy,...
A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 μm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a small-signal power gain of 16.2 dB, a maximum...
A fully integrated CMOS receiver consisting of an LNA and a mixer has been designed and fabricated in IBM BiCMOS 7WL 180 nm technology. An on-chip balun loading the second stage of the LNA was implemented as well for single-to-differential conversion. The receiver was developed for high performance wireless local positioning systems and excellent experimental results were demonstrated: a conversion...
A digitally controlled variable gain amplifier (VGA) for low power, low-IF receivers is presented. The amplifier was designed and fabricated in IBM 7WL BiCMOS 180 nm technology. It shows a dynamic range of 45 dB with a maximum gain of 52 dB and a minimum gain of 7 dB. The gain variation is achieved by means of switched feedback resistors. These are controlled by a demultiplexer and 4 control bits...
Modern wireless communication standards, e.g. UMTS, are making use of modulation schemes, resulting in signals with high levels of peak-to-average power ratio (PAR). For example, the W-CDMA signal used in UMTS-standard has typical PAR levels above 6 dB. Conventional single-ended power amplifiers will result in low levels of average efficiency, if they were implemented in the transmitters of such communication...
In this work we present a fully integrated BiCMOS RF-receiver. The receiver comprises an LNA and a mixer. The most challenging aspects of the design were the high gain and an extremely low noise figure specified by RESOLUTION. The target was to achieve an integrated LNA and mixer showing at least 25 dB voltage conversion gain and overall noise figure less than 4 dB under minimum power consumption...
This paper describes the design of an integrated frontend module, suited for reliable 60 GHz transmission. The module makes use of a recent SiGe chip set presented and it is based on a commercial available high volume printed circuit board technology. In the following we focus on the frontend architecture, the on-board antenna and the transitions between board and chips.
Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of-3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported...
This work demonstrates an integrated low noise, high gain receiver targeted for wireless local positioning applications. The receiver is implemented in a 0.18 mum SiGe BiCMOS technology. With a single ended input and differential output the receiver comprises a two stage bipolar low noise amplifier with integrated on-chip transformer for single to differential conversion and a double balanced mixer...
A 60 GHz SiGe HBT chipset for high speed wireless communication systems has been developed. The functionalities of LNA, up-converter, down-converter and PA have been realized with good performance. Design strategy, achieved results and comparison with state-of-the-art work will be presented. The work proves that single chip integration of the whole 60 GHz RF-frond-end will be possible using silicon...
A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal...
A folded double-balanced mixer has been implemented in a 0.18 mum BiCMOS technology for wireless local positioning applications. Operating in the unlicensed ISM band centred at 5.8 GHz with a 150 MHz bandwidth and with a very low IF frequency band from 500 kHz up to 5 MHz, the mixer achieves 17 dB voltage conversion gain, 8.5 dB noise figure and input IP3 of - 6 dBm. The mixer power consumption is...
A two stage bipolar low noise amplifier based on common-emitter configuration is presented in this work. From transistor size scaling to complete two stage integration, various design aspects and issues will be investigated. It will be shown that by following the proposed design methodology, the input as well as the interstage matching of the low noise amplifier (LNA) can be highly simplified without...
In this work we report on the importance of electromagnetic analysis for the layout design of monolithic 60 GHz power amplifiers (PA) in SiGe HBT technology. To facilitate this, two different layouts of the same circuit architecture were investigated. The circuits were originally designed using the circuit simulator of Agilentpsilas ADStrade and realized in a high performance 0.25 mum SiGe BiCMOS...
A monolithic low-noise-amplifier operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 mum SiGe BiCMOS technology, featuring npn transistors with fT and fmax ap 200 GHz. A two stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a gain of 18 dB at 61 GHz,...
FinFET technology presents a competitive alternative to planar CMOS as it features a better control of the short channel effects. This results in improved digital and analog performances. The radio-frequency (RF) behavior is however affected by a large level of parasitics. In this paper, we explain how technological options and device design affect the FinFET performance. In addition, the challenges...
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