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In this paper, a new ultra-thin body and BOX (UT2B) fully-depleted (FD) silicon-on-insulator (SOI) device architecture based on a stacked back plane (BP) and WELL below the BOX is presented. The proposed device has been developed to boost the gate-to-channel electrostatic control and to be compatible with the adaptive body biasing (ABB) techniques for low power applications. The concept viability...
This study aimed to investigate, among a sample of elite Australian athletes, the extent to which this group supports drug testing as a deterrent to drug use.Data was collected from a convenience sample of (n=974) elite Australian athletes who self-completed a questionnaire, and semi-structured telephone surveys with key experts.The athletes surveyed endorsed testing for banned substances as an effective...
A low-cost and high-manufacturability Multi-VT Ultra-Thin BOX and Body (UT2B) FDSOI technology is proposed for high-performance and low-leakage digital circuits. This concept allows setting up low, standard and high threshold voltage (VT) devices without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. Device electrical characteristics, process flow...
In this paper, an original and simple concept for setting up multi-VT for fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. Low, standard and high threshold voltage (VT) devices are achieved without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. The concept is based on the use of a thin buried oxide (BOx) combined with the integration...
In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45 nm technology node. The stability of the cell reaches 20% of VDD and the cell leakage is 13 pA. A minimum cell area of 0.209 mum2 with specific 45 nm SRAM design rules...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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