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System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for miniaturization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of...
The challenges of 3-D integration are its sophisticated processes that require deposition, etching, bumping, plating, thinning, etc., which drive the need for wafer bonding materials that can sustain the high temperatures and chemically stringent environments found in these processes. This paper presents the development of a novel polymer material to be used as a wafer bonding material suitable for...
Through silicon via (TSV) is a very attractive solution for 3D stacking. Currently the main technique in industrial TSV processes is the via-last approach. But the via-first approach has also many advantages and in particular allows the use of high thermal budget materials for high voltage applications. In this work, we will show results on process development and integration of 100 mum deep annular...
In this paper, an original way to open buried contact in TSV via-last process using dry film lithography will be presented. This approach may solve at the same time issues on either non tapered vias and sloped vias technologies. In the first part of the paper the via-last process flow and the technological issues will be briefly described. Then the contact opening lithography using dry film will be...
In this paper, the via-last TSV process using dry film lithography will be presented. Historically we used dry film resist (DFR) for the copper rerouting (via metallization) step only, but here we also tried implementing it for via etching. In the first part of the paper the via-last process flow will be briefly described. Then the copper rerouting lithography using dry film will be presented. This...
In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front...
In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps...
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