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As radio frequency microelectromechanical systems (RF-MEMS) mature as a manufacturable technology, packaging of the devices becomes increasingly important. Devices such as aluminum nitride (AlN) RF-filters require packaging which is either hermetic or under vacuum to protect the devices [1]. It then becomes critical to have a measurement of pressure inside the packaged chamber. Typically for this...
This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly...
In this paper, an original way to open buried contact in TSV via-last process using dry film lithography will be presented. This approach may solve at the same time issues on either non tapered vias and sloped vias technologies. In the first part of the paper the via-last process flow and the technological issues will be briefly described. Then the contact opening lithography using dry film will be...
In this paper, the via-last TSV process using dry film lithography will be presented. Historically we used dry film resist (DFR) for the copper rerouting (via metallization) step only, but here we also tried implementing it for via etching. In the first part of the paper the via-last process flow will be briefly described. Then the copper rerouting lithography using dry film will be presented. This...
In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front...
In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps...
The electron beam direct write (EBDW) lithography solution is already mature enough to be used for semiconductor manufacturing. This paper illustrates the potential of EBDW to support technology development as a patterning technique complementary to the projection optical lithography. The first classical application of EBDW lithography is to support the research and development efforts (R&D) well...
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