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In this paper, the skin effect of on-chip transmission lines and inductors at K-Band operating frequencies are investigated. Two microstrip lines with different lengths are simulated and compared with each other. A patterned ground shielded inductor is simulated using various meshing strategies and the results are compared. A 24 GHz common source CMOS low noise amplifier is designed, simulated and...
In this work we present a fully integrated BiCMOS RF-receiver. The receiver comprises an LNA and a mixer. The most challenging aspects of the design were the high gain and an extremely low noise figure specified by RESOLUTION. The target was to achieve an integrated LNA and mixer showing at least 25 dB voltage conversion gain and overall noise figure less than 4 dB under minimum power consumption...
Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of-3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported...
A 60 GHz SiGe HBT chipset for high speed wireless communication systems has been developed. The functionalities of LNA, up-converter, down-converter and PA have been realized with good performance. Design strategy, achieved results and comparison with state-of-the-art work will be presented. The work proves that single chip integration of the whole 60 GHz RF-frond-end will be possible using silicon...
A two stage bipolar low noise amplifier based on common-emitter configuration is presented in this work. From transistor size scaling to complete two stage integration, various design aspects and issues will be investigated. It will be shown that by following the proposed design methodology, the input as well as the interstage matching of the low noise amplifier (LNA) can be highly simplified without...
Target of this work is to explain the significance of electromagnetic effects due to on-chip spiral inductors and passive interconnects on the circuit behavior. Starting from the design aspects of spiral inductors in a cascode CMOS LNA, the influence of their on-chip coupling on the reverse isolation performance of the amplifier will be presented. The importance of the careful consideration of on-chip...
A monolithic low-noise-amplifier operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 mum SiGe BiCMOS technology, featuring npn transistors with fT and fmax ap 200 GHz. A two stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a gain of 18 dB at 61 GHz,...
This work demonstrates the design of a wideband low noise amplifier in 0.13 um CMOS technology. Important design aspects and the influence of bandwidth improving circuit elements on various LNA performance parameters like gain, matching, noise figure, and stability are analyzed. Simulated and measured LNA results are presented. At the centre frequency of 5.5 GHz the measured LNA performance includes...
This work presents a fully integrated 6 GHz LNA designed using 0.12 mum IBM CMOS technology. The amplifier consumes only 3.6 mW dc power with 1.2 V supply voltage, and features a 11 dB power gain and 3.6 dB noise figure at the frequency of 6 GHz. Additionally, it achieves -11 dBm of input referred 1 dB compression point and -0.5 dBm of IIP3. At the same time input and output matching are better than...
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