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In this letter, a hybrid modulation concept consisting of three-level space vector modulation (3L-SVM) and phase-shifted pulse width modulation (PS-PWM) is proposed for five-level active-neutral-point-clamped (5L-ANPC) converter. Under this concept, a simpler 3L-SVM plus PS-PWM scheme is applied to realize 5L modulation, instead of using complex 5L-SVM. The control of neutral voltage, flying capacitor...
In single-phase photovoltaic (PV) systems, power mismatching between input and output terminal leads to power pulsation, seriously affecting maximum power point tracking (MPPT). Paralleling an electrolytic capacitor (e-cap) across PV panel to smooth power pulsation seems to be an unreliable method owing to its short lifetime. Various power decoupling methods used in micro-inverters have been proposed...
In this paper, a modulation strategy based on zero-sequence voltage injection is proposed for module multilevel converter (MMC). By the proposed method, the remaining capacitor voltages not vary and the line-to-line voltages are balanced. This method is easy to be implemented by adjusting the voltage injection coefficient when SM fault occurs. The coefficient of injected zero-sequence voltage is designed...
Z source inverter overcomes the shortcomings of the traditional voltage source and current source, but its DC side current is not continuous, the voltage utilization is low and the boost factor is limited. In recent years, some scholars have proposed a new inverter — switching boost inverter (SBI). Compared with the traditional Z source inverter, the boost factor of SBI is reduced, but the cost and...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
An off-chip capacitor-free CMOS low-dropout voltage regulator (LDO) for full on chip power management solution is presented. The proposed structure based on modified nested Miller compensation and transient enhancement network provides both fast load transient response and full load stability. For a pulsed load current between 0.5 mA and 50 mA, it is able to recover within ~3.5 mus and a less than...
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