A low noise and wide tuning range integrated phase-locked loop (PLL) was proposed. Besides careful design of the low noise and wide tuning range voltage-controlled oscillator, a large loop bandwidth was chosen to suppress the phase jitter contributed by the voltage-controlled oscillator. In addition, a charge pump capable of improving the switching time mismatch and the dynamic current mismatch was proposed to further reduce the jitter and reference spurs in the PLL. Based on a 0.18 µm CMOS process with 1.8 V supply, the transient simulations and phase noise simulations of the PLL were performed. The transient simulation results verified that the tuning range of the PLL was from 80 MHz to 720 MHz. The phase noise simulation results showed that the PLL achieved a period jitter of 0.44 ps and a reference spur of −120 dBc at the output frequency of 480 MHz.