In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through the resolution bottleneck of the delay chain approach, a TIM structure is adopted by utilizing the dedicated carry chain of FPGA. To verify the proposed method, we implement a multi-chain TIM circuit which consists of 16 chains in the Kintex-7 filed-programmable-gate arrays (FPGA). The post-route simulation results show that the bine size can be increased to 1.67ps and the RMS is enhanced to 3.99ps without bringing extra dead time. In addition, the proposed method is able to make full use of the delay unit, which reduces the hardware cost of the circuit by nearly 35% compared to the previous method.