Integrating analog-to-digital converters that utilize a phase-sensitive detector (PSADCs) are frequently used in high precision instrumentation and measurement systems. As any technical object, a PSADC is subject to faults. These faults must be detected promptly and accurately by built-in low complexity hardware. In the present work, this objective is achieved by the adoption of error-control codes. Off-line and on-line test methods are explored. We demonstrate how to perform compaction in digital and analog domains. We design a compactor of analog signals on the basis of a PSADC and explain how to utilize coding redundancy for on-line testing. We also explain how to use a PSADC for generating multiple residues which can further be processed by a computing device operating in a residue number system (RNS). Compared to existing techniques, the proposed approach is characterized by higher accuracy and lower latency. The proposed device can be used for analog circuits testing in much the same way as a conventional signature analyzer is used for digital circuits testing. The test process involves measuring signatures of analog signals, which ultimately appear in digital form. The signatures are then verified to make a pass/fail decision.