Integrated digital circuits are frequency capped by its heavily constrained paths between flip-flop stages. These so-called critical paths are highly susceptible to delay fluctuations leading designers to use guard-banding in order to avoid timing violations. Several effects can cause these variations, whereas aging is of rising importance. Many works have addressed this issue through monitoring of critical paths or techniques for error detection. The consequent error correction, however, requires the interruption of the circuit's operation for restoration of correct values, resulting into a performance drop. This work proposes two strategies tackling this problem without cycle loss: A time-borrowing approach that redistributes the slack between a critical path and its most constrained fan out paths; and the technique Alternative Path Activation (APA) which applies duplication of the most time-constrained fan out paths of a critical path. Simulations were conducted for several test circuits indicating its feasibility. Further, the proposed approach was implemented in ARMv2 based processor core, resulting in an enhanced robustness against aging induced delay variations of 7.2 % at the cost of 2.5 % area and 2.7 % power overhead.