Bottom-gate thin-film transistors (TFTs) are currently fabricated using either a three-mask back-channel-etched (BCE) or, with an additional mask for the definition of an etch-stop (ES) layer, a four-mask technology. The former offers a lower cost of manufacturing and a higher resolution, while the latter provides better device characteristics in terms of both performance and reliability. Presently reported is a three-mask process for realizing an elevated-metal metal-oxide TFT employing self-aligned patterning of the active island, also inherently incorporating an ES layer. This technology offers a TFT that combines the same protection of the channel, and hence, the good characteristics of an ES TFT, with the lower cost, reduced parasitic overlap capacitance, and smaller device-footprint of a BCE TFT.