The semiconductor packaging technology trend for electronic products continues to achieve greater miniaturization and higher functionality. Thinner profile chip scale packaging (CSP), such as flip chip CSP (fcCSP), with increasing die complexities is a very important technology for next generation communication devices and internet of things (IoT) applications. Recently, integrated fan out wafer-level packaging (FOWLP) technology has received increased attention as one of next generation solutions in this field. This is due to its unique ability to achieve extremely thin profile and less warpage for Package-on-package (PoP) configurations as well as higher electrical performance. However, this bottom-up wafer level technology is still cost ineffective and has issues that, so far, have prevented it from becoming a mainstream technology in existing outsourced semiconductor assembly and test (OSAT) facilities. Hence, there has been increased need for thin profile flip chip technology. Despite the demands, the conventional interconnection method using a mass reflow (MR) process has had predictable limitations for bump and pad pitch shrinks and it could not support interconnections with very thin die and coreless substrates. To overcome the MR process technical limitations, recent research has focused on developing various interconnection or soldering process technologies that utilize different heat transfer mechanisms to minimize the thermal stress. This paper will discuss laser assisted bonding (LAB) technology for enabling extremely thin profile flip chip package with coreless substrate as a next generation interconnection solution and how it to control the heat energy can be controlled versus conventional MR process. This LAB process offers a very stable interconnection quality as well as robust functional and reliability test results. In additions, it will be described further advantage of LAB for the next generation devices.