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In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters " (ANC) requires an extremely simple additional...
System-in-package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered...
The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15...
This paper describes a variance reduction technique for supply ramp test method. The technique makes use of multiple current measurements from a single device under similar test conditions to generate robust test limits with lower variance. The necessary conditions that guarantee variance reduction under these circumstances have also been described. We demonstrate that variance reduction has an additional...
PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, output frequency, duty cycle, and other parameters. Its multi-GHz range, sub-picosecond jitter noise floor, and minimal...
Delay testing is mandatory for guaranteeing the correct behavior of today's high-performance microprocessors. Several methodologies have been proposed to tackle this issue resorting to additional hardware or to software self test techniques. Software techniques are particularly promising as they resort to Assembly programs in normal mode of operation, without requiring circuit modifications; however,...
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of Systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests...
The growth in system-on-chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip through to the stage when silicon and the complete software stack are first brought together. Finding the remaining errors at this stage is becoming increasing difficult. We propose that debugging should be communication-centric...
SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory. SEUs may have critical effects on the circuit FPGA devices implement. In order to deploy safety- or mission-critical applications on SRAM-based FPGAs, designers need to adopt hardening techniques, as well as methodologies for estimating and validating the SEU's sensitivity...
The evolution of the technology in search of smaller and faster devices brings along the need for a new paradigm in the design of circuits tolerant to soft errors. The current assumption of transient pulses shorter than the cycle time of the circuit will no longer be true, thereby precluding the use of most of the mitigation techniques proposed so far. With transient faults duration spanning more...
LFSR reseeding forms the basis for many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects. We use the recently...
Despite the recent advances in ATPG technology computing test patterns for state-of-the-art industrial designs can demand an enormous amount of computation time. Numerous structural techniques were presented to reduce the search space and hence the runtime of state-of-the-art ATPG tools. Absolute dominators introduced by Kirkland and Mercer proved to be useful for finding mandatory observation nodes...
We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These...
The following topics are dealt: fault and defect diagnosis; mixed signal DFT and test; NOC testing; RF test; diagnosis and debugging; circuit simulation and verification; memory test; on-line testing; self-testing; fault grading and test quality; diagnosis and yield improvement; single event upsets; BIST; and delay and performance test.
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