A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ration of only 32. This modulator is implemented with fuly differential swith-capacitor circuits and is manufactured in a 2-μm BICMOS process. The converter achieves 97 dB...
The Redundant Signed Digit (RSD) algorithm has been successfully applied to cyclic and pipeline analog to digital converters [1][2]. It is superior to the Convertional Restoring (CR) algorithm regarding cancellation of offset errors, speed and an additional bit. In this paper, we consider the advantages resulting from an implementation in a current-mode pipeline analog to digital converter.
A 10-bit 5MS/s successive approximation ADC cell is presented. With a clock frequency of 70MHz, the sampling time is limited to 14nS, which is aimed for a parallel ADC array. A two-step principle based on unsymmetrical dualcapacitor charge-redistribution-coupling has been used. The comparator with the help of reset function presents a fast response to the successive comparison. The core of the ADC...
The design of an 8-bit CMOS ADC is described which is intended for embedded operation in VLSI chips. The requirements on accuracy are analyzed and a new comparator circuit realizes the high bandwidth. The full-flash architecture operates on wide-band signals like CVBS in television systems. The ADC core measures 2.8 mm2 in a 1 ??m CMOS process.
A single 5V, 6-bit Flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The design of the converter is optimised to operate in under-sampling applications where the ADC has to maintain performance with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies of up to 75MHz and a gain flatness of better...
This paper describes a high-speed D/A conversion system with an embedded 5-bit programmable FIR filtering function suitable for applications in video interfaces. For demonstration purposes a prototype chip has been fabricated in a digital 1.2 ??m single-poly CMOS technology for realizing the combined functions of an 8-bit current-steering D/A conversion and a 3-tap color carrier suppression filtering...
In this paper we present a new architecture for a smart sensor interface. It is based on an oversampled A/D converter associated with a small ROM containing calibration coefficients. The non-linear function desired is obtained by piecewise linear interpolation between the values stored in the ROM. This solution has the advantages of high programming flexibility, long-term stability and low area consumption...
A discrete-time approach to the simulation of current-memory ??-?? modulators is presented. The simulator takes into account non-idealities such as charge injection and noise in a very precise model of the current-memory cell. It has been used to evaluate the performance of a 2nd order ??-?? modulator designed in a 1.2 ??m CMOS technology.
Two-dimensional power-line selection scheme for an iterative CMOS circuit block, is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks of two-dimensional arrangement and selectively energized by two-dimensional power-line selection. The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth, from 363 mA...
A new high-density memory cell concept for storing analog information as well as digital data is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor generates a large bit-line signal voltage at a supply voltage as low as 1.0V. Since this cell does not need a large storage capacitance and the pass-transistor can be stacked on the top of the amplifying...
This paper proposes a new array architecture named extended second metal line (ESL) architecture, in which second metal line is used as not only power lines for distributed sense-amp drivers but global data-buses in the memory array. The self-recovering Vpp generator for output driver is further described to ensure the output high level in fast column access modes. By using the proposed array and...