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A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
Stochastic turbo decoder is a new scheme for turbo codes. But the long decoding latency and high complexity are two main challenges for fully parallel stochastic turbo decoders. In this paper, we proposed a novel stochastic turbo decoder scheme with two high accuracy stochastic operator modules, including no-scaling stochastic addition and stochastic normalization operator, which can improve the decoding...
Memristor technology is receiving an increased attention as a potential solution to meet the scaling demands in integrated circuit design. Memristor provides advantages like high-density, low-power, non-volatility and good scalability. In this paper, an 8-bit iterative full adder design is proposed that uses space-time based circuit notation. It uses stateful logic with memristive nanowire crossbar...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout...
This paper proposes a 1-1 MASH ΔΣ time-to-digital converter (TDC). A cascode time adder with a raised inverter threshold voltage is proposed to minimize the jitter caused by current mismatch. A differential time integrator consisting of two single-ended time integrators is proposed to minimize even-order harmonics. The detrimental effect of the nonidealities of the TDC is examined in detail. The TDC...
This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
Approximate computing is gaining increasing interest among the VLSI design community due to its potential for enabling low power, high speed, and less area while delivering acceptably correct computation results for many digital signal processing applications. In this context, this paper considers for the first time asynchronous quasi-delay-insensitive (QDI) realizations of approximate adders which...
Two Band-Pass (BP) Discrete Time (DT) ΔΣ modulators are proposed in this paper. In both cases, the drawback of high-speed power-hungry adder is tackled by proposing a modified unity signal transfer function (STF) adder-less feedforward structure. The first proposed BP DT ΔΣ modulator is a conventional adder-less multi-stage noise shaping (MASH) ΔΣ modulator, while the noise leakage problem, caused...
In this paper, a novel neural network architecture is proposed which results in an area-efficient feed-forward network. These structures require high-resolution multipliers. In order to overcome this problem, a mixed-signal Multiplying Digital to Analog Converter (MDAC) architecture which employs Delta-Sigma Modulation (DSM) to encode the multiplication results into the time domain. The time-domain...
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