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This brief presents the SoC-FPGA implementation of the modified Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm. The implementation was carried out by using hardware/software co-design based on software profiling that helped to find out that pseudo-random Spectral Permutation, Windowing, and Sub-Sampling (SPWS) are the signal processing operations that require most processing time in...
This work presents an embedded computing framework for the analysis and design of large scale algorithms utilized in the estimation of acoustic doubly dispersive, randomly time-variant, underwater communication channels. Channel estimation results are used, in turn, in the proposed framework for the development of efficient high performance algorithms, based on fast Fourier transformations, for the...
In Gradient-Based Cross-Spectral Stereo Matching (GB-CSSM) output disparity maps tend to produce coarse results that are, for the most part, reliable. However, general methods of improving the performance of disparity maps generated from the Cross-Spectral comparison of visual and full infrared input images are non-existent. In particular, previous works fail to address the role and interaction of...
For autonomous medium power (1–10 W) field systems deployed in off-grid applications without established power infrastructure, two system design criteria are crucially important: i) continuous availability of power, ii) robust and low-maintenance operation. In this paper, we provide circuit and system designs for energy harvesters that address both issues by utilizing supercapacitors as their energy...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
Timing leakage can be exploited to break a cryptographic system. Even though timing attacks have been well-researched for the past decade, recent system implementations remain highly vulnerable to these attacks. There is a critical need to develop a framework for automatic evaluation of vulnerability of a design against these attacks, so that integrated circuit designers can understand the vulnerability...
Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware...
A robust calibration and supervised machine learning reliability framework has been developed to aid the circuit designer in the design and implementation of reliable digitally-reconfigurable self-healing RFICs. For calibration algorithm performance and reliability validation, we advocate the use of surrogate modeling, a supervised machine learning technique, which offers a significant reduction in...
In this paper, the minimum total required transconductance for the different architectures of the pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. It is shown that the Algorithmic-Pipelined ADC requires a simpler Sub-ADC and shows lower sensitivity to the Multiplying...
An aggressive controlling for layout pattern density is becoming essential for the manufacturability of advanced processes. Focusing on analog layout under severe density constraints, this paper provides a novel idea that layout generation and verification are co-working on a density-aware format. Our idea follows a transistor-array(TA)-style of analog layout where unit-transistors of the same channel-size...
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