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Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel...
The performance of superdirective beamforming of a practical circular hydrophone array is investigated. The received signal of a 16-element circular hydrophone array with radius of 0.25m are measured in the anechoic water tank. The array manifold at the frequency of 1.11kHz is obtained. The superdirective beamforming of the circular array is designed and realized. The correctness and effectiveness...
A novel multi-dimensional noise-shaping method is proposed to extend Δ-Σ modulation to the two-dimensional (2-D) (space, time) case. It uses spatial oversampling to provide another degree of freedom for ADC designers to shape quantization noise when temporal oversampling is limited. The method uses lossless discrete integrators (LDIs) to implement spatial integrators and is suitable for use in microwave...
For a growing pool of data-intensive applications, data transfer, rather than processing speed, has emerged as the major bottleneck to performance and energy scalability. In this paper, we propose a novel interleaved logic-in-memory architecture, referred to as MISK, which leverages fine-grained integration of logic functions within dense, 2-D static random-access memory (SRAM) arrays for in-situ...
A general methodology of device array mismatch characterization is introduced, analyzed and verified. Instead of measuring each device's parameter individually, the device array is configured as a data converter and the mismatch information is extracted from the differential linearity (DNL) of the converter. Systematic and random mismatch are characterized separately using the proposed decomposition...
Gradient errors in device arrays cause mismatch between device parameters, which in turn degrade linearity performance of data converters realized with these arrays. A practical “outputs averaging” technique for string DACs is presented to release complex routing problems in gradient reduction patterns. An N-bit string is divided into multiple substrings and the substrings' outputs are averaged to...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
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