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This paper presents a CMOS image sensor with high conversion-gain pixels and column-shared pipelined ADCs for Fluorescence-lifetime imaging microscopy (FLIM). Pixel conversion gain of 121 uV/e-is achieved by creating a distal floating diffusion from transfer gate and reset transistor gate without any process modification. 32-channel 10-bit on-chip column-shared pipelined ADCs with sampling rate up...
The flipped voltage follower (FVF), a variant of the common-drain transistor amplifier, comprising local feedback, finds application in circuits such as voltage buffers, current mirrors, class AB amplifiers, frequency compensation circuits and low dropout voltage regulators (LDOs). One of the most important characteristics of the FVF, is its low output impedance. In this tutorial-flavored paper, we...
This paper presents a novel multimodal CMOS based biosensor consisting of integrated capacitive and thermal sensors for Lab-on-Chip applications. A new capacitive sensor is also proposed which converts the capacitance changes to frequency by using a current-controlled oscillator. This sensor works based on charge based capacitance measurement (CBCM) technique. Its operation in current mode helps this...
This paper investigates a class of electrical generators based on capacitors and diodes, with two capacitors being variable. Their main characteristics are a symmetrical structure and that they produce two outputs with the same polarity. The simplest version is analyzed in more detail, although in an approximate way, and generalizations of it are obtained, identified with a particular form of two-phase...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
This paper presents the design of a zero-voltage-ripple (ZVR) buck dc-dc converter. The circuit uses an autotransformer for ripple cancellation in the output voltage. The principle of operation is discussed in brief. The relationship between the currents through the magnetizing inductance and the auto-transformer windings is developed. The auxiliary inductance for ripple cancellation in series with...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency...
An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing...
Locally NOR and globally NAND match-line architecture and sensing circuits applicable to the high performance content addressable memory(CAM) is proposed in this paper. As word-length of CAM gets longer, the capacitance of match-line gets larger and it causes performance degradation and large dynamic power consumption. Local match-lines are segments of large capacitive match-line and designed as NOR-type...
In this paper, the sensitivity of the optical receiver is revisited. An analytical expression that reveals the dependency of the sensitivity on both the data rate (fbit) and the bandwidth shrinkage factor (n) is derived. The proposed sensitivity model provides guidelines for selecting the front-end topology. Based on that model, a three-stage front-end is implemented in 65 nm CMOS technology and 18...
In this paper, an electronically tunable immitance circuit is proposed. The presented circuit can be configured as a tunable grounded inductor or capacitor multiplier. The proposed circuit employs a single active element called Voltage Differential Current Conveyor, a single resistor and a single capacitor. The presented circuit does not require element matching constraints. It is linearly tunable...
Low-dropout voltage regulators (LDOs) have been extensively used on-chip to supply voltage for various circuit blocks. Digital LDOs (DLDO) have recently attracted circuit designers for their low voltage operating capability and load current scalability. Existing DLDO techniques suffer from either poor transient performance due to slow digital control loop or poor DC load regulation due to low loop...
This paper presents a comparative study of dual-adaptive DFE for 4PAM serial links with a reduced number of error slicers. Two set of SS-LMS DFE, one for optimal DFE tap coefficients and the other for optimal reference for error generation are employed. The data-dependent nonlinear characteristics of channels and their effect on the choice of the reference for error generation are investigated. We...
This paper discusses an analytical method for performance estimation of multi-stage transimpedance amplifier (TIA). For high speed and energy efficient optical communication, multi-stage TIA composed of pre-amplifier (PA) and Cherry-Hooper amplifier (CHA) are commonly used. However, it is not clear how to decide design parameters of PA and CHA. Additionally, the number of stages is also a design parameter...
The mechanism by which the frequency of an LC VCO is sensitive to the power supply is analyzed. It is shown that variations in both the common-mode and differential-mode components can give rise to periodic jitter in the presence of supply variations due to capacitive nonlinearities. A new compensation method that reduces this sensitivity is presented. Simulations are shown verifying that this method...
In this paper, an advanced layout scheme of an integrated capacitor is presented which improves the efficiency of a poly-poly capacitor based voltage doubler charge pump. The main losses in voltage doubler charge pumps are mathematically described and the importance of low stray capacitances are discussed. By means of the improved poly-poly capacitor layout, the usable capacitance is increased while...
Memelements — circuit elements with memory — serve novel applications in several technical disciplines. Due to similar functionalities to synapses, they are especially suitable for neuromorphic circuits. Physical and chemical phenomena in the nano-scale lead to the unique information storage characteristic of these elements. Fabrication of devices with memory considering a particular desired functionality...
This paper reports a low-power low-noise folded-cascode OTA based charge amplifier designed to be used as the front-end amplifier (FEA) for a pyroelectric transducer based respiration monitoring system. The amplifier is designed in 0.5μm standard CMOS process and consumes only 5.4 μW of power with 1.8V supply voltage. The operational transconductance amplifier (OTA) adopts a pseudo-resistor based...
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