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We propose μLeech, a new embedded trusted platform module for next generation power scavenging devices. Such power scavenging devices are already widely deployed. For instance, the Square point-of-sale reader uses the microphone/speaker interface of a smartphone for communications and as power supply. While such devices are used as trusted devices in security critical applications in the wild, they...
This paper presents a novel multimodal CMOS based biosensor consisting of integrated capacitive and thermal sensors for Lab-on-Chip applications. A new capacitive sensor is also proposed which converts the capacitance changes to frequency by using a current-controlled oscillator. This sensor works based on charge based capacitance measurement (CBCM) technique. Its operation in current mode helps this...
This paper investigates a class of electrical generators based on capacitors and diodes, with two capacitors being variable. Their main characteristics are a symmetrical structure and that they produce two outputs with the same polarity. The simplest version is analyzed in more detail, although in an approximate way, and generalizations of it are obtained, identified with a particular form of two-phase...
Efficient and smart techniques for analog data acquisition and processing may play crucial role in the design of miniature wearable devices, meant to continuously record, process and wirelessly transmit vital physiological parameters for real time health monitoring. In this work we propose a low-power, all-analog processing unit for an MPG (magneto-plethysmograph) based wearable device, which is meant...
In this paper we present circuit techniques to optimize analog neurons specifically for operation in memristive neuromorphic systems. Since the peripheral circuits and control signals of the system are digital in nature, we take a mixed-signal circuit design approach to leverage analog computation in multiplying and accumulating digital input spikes and generate binary spikes as outputs to be consistent...
The ever-increasing need for higher number of neural recording channels along with the stringent power and area requirements of a brain-implantable device, demand for ultra-compact and scalable channel architectures. In this paper, we will first briefly discuss the fundamental scaling issues of conventional AC- and DC-coupled neural front-ends. Next, we will analytically examine the feasibility of...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
Ferroelectric RAM (FRAM) is a non-volatile memory with fast, low power, high endurance, read and write operations. Hence, this technology remains an attractive choice for embedded system solutions. In this paper, we analyze Si data that initiated the effort to design a compensated Sense Amplifier (SA) with improved input offset-sigma. We evaluate the cost vs benefit tradeoffs associated with this...
Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU...
In this paper, we illustrate, through examples, a novel graph-based modeling technique of two-state (on-off) PWM power converters. Differential equations of power converters are derived by inspection, based on two incident matrices, β(u) and J(u). We associate to each circuit (on, u = 1, or off, u = 0, circuits) a digraph and identify current loops (inductor-capacitor, voltage source-inductor, current...
The Sun has the potential to provide 89,300 tera Watts of power to our planet. Our ability to convert even a fraction of this energy for human use makes a significant impact on current energy generation and consumption trends. World-wide we now add more renewable energy capacity every year than (combined) fossil fuel energy capacity. Solar panels provide a reliable, renewable, non-polluting energy...
In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation,...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
This paper is on the study of double coupled oscillators, where two cross-coupled differential oscillators share the same bias current. Without external coupling, competition for bias current happens, and the one with a higher Q can grab most of the current, and the other one is starved to death. With external coupling, a beat pattern is generated and the beat frequency is strongly related to the...
A CMOS Crystal Oscillator with automatic amplitude control (AAC) is presented which occupies low area and consumes lower current when compared to existing state of the art designs. Amplitude control loop based implementations of low frequency crystal oscillators usually achieve low-power operation at the expense of die area. The proposed design aims at reducing the overall area by replacing the bulky...
In this paper, an electronically tunable immitance circuit is proposed. The presented circuit can be configured as a tunable grounded inductor or capacitor multiplier. The proposed circuit employs a single active element called Voltage Differential Current Conveyor, a single resistor and a single capacitor. The presented circuit does not require element matching constraints. It is linearly tunable...
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