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A platform has been developed to study intercellular communication in non-neural cells as it relates to developmental biology and morphogenetic bioengineering. The versatile platform uses laminar flow in a microfluidic channel to create a “sucrose gap” that forces electrical signaling through a cell monolayer. The intercellular communication in the cell network is detected through electrical impedance...
This paper presents a monolithically implemented NFC bicycle tire pressure measurement system (BTPMS) with integrated antenna, on-chip capacitive pressure and temperature sensor, RFID interface for HF/NFC and EEPROM. This NFC BTPMS has been designed using a 130 nm standard CMOS process and has an active chip area of 5.76 mm2. It provides significant cost advantages and impresses with its large scale...
Compressive sensing (CS) is a recent signal processing paradigm that exploits the inherent sparsity in input signal through data compression before wireless transmission. Recent CS implementations have shown impressive energy-efficiencies with good signal recovery but require apriori sparsity estimation and are thus not adaptable dynamic IoT environments resulting in loss of accuracy. This paper describes...
In this study, CMOS-based on-chip neural interface devices with integrated optical stimulation capability are presented. The devices are designed for use in optogenetic applications. Two types of neural stimulators are presented. In one type, the on-chip CMOS image sensor was integrated with blue LEDs. Variations of device structures were developed as well. An in vivo experimental demonstration using...
A CMOS integrated frequency domain near infrared spectroscopy (fdNIRS) and transcranial direct current stimulation (tDCS) is designed for simultaneous brain stimulation and monitoring. The combination of optical sensing and electrical stimulation solves the incompatibility between EEG and tDCS in both time and spatial domains. A real-time closed-loop brain stimulation can be realized for neurological...
A fourth-order Butterworth active Gm-C complex IF filter for dual-mode GNSS receiver is presented. This filter operates at center frequency of 7.161MHz and in bandwidth of 4MHz with pass-band gain of over 10dB and image rejection of over 35dB, which meets requirements of BD2 and Galileo Systems. The proposed CMOS fully differential transconductor has wide tuning range, high linearity and low power...
This paper proposes a novel fully differential ultra-low voltage transimpedance amplifier (TIA) based on a CMOS translinear circuit. Following a simple bias strategy, its transimpedance gain can be adjusted to the desired accuracy either by means of an external resistor or using internal voltage and current references. To a first order approach, the transresistance results independent from technological...
This paper reports a low-power low-noise folded-cascode OTA based charge amplifier designed to be used as the front-end amplifier (FEA) for a pyroelectric transducer based respiration monitoring system. The amplifier is designed in 0.5μm standard CMOS process and consumes only 5.4 μW of power with 1.8V supply voltage. The operational transconductance amplifier (OTA) adopts a pseudo-resistor based...
Optical systems-on-chip (SOCs) with integrated optical passives in the visible and near-IR range can have a tremendous impact in miniaturizing complex optical instrumentation to enable a new class of ultra-compact, low-cost optical sensors and imagers for a wide variety of emerging applications. However, while high-density image sensors are now commonplace in CMOS, all passive optical components are...
In this paper, a programmable precise time delay generator suitable for a beam forming impulse ground penetrating radar (GPR) is presented. The design is based on a phase locked loop (PLL) circuit that is implemented utilizing Global Foundries 7HV 0.18μm CMOS process. The precise time control realizes the true time delay, which allows for developing an ultrawide band (UWB) phased array GPR system...
This paper presents a CMOS 65 nm optical receiver design based on a continuous-time feed-forward equalizer (CT-FFE). A low-bandwidth front-end approach increases the mid-band gain and improves sensitivity. However, the intersymbol interference (ISI) that is introduced must be removed using equalization. The proposed CT-FFE topology mitigates the challenges of sampling present in discrete-time FFEs...
This paper describes two approaches to increase the energy efficiency of on-chip terahertz (THz) integrated circuits and systems. First, we present designs of multi-functional electromagnetic structures that utilize mode orthogonality and near-field interference to achieve simultaneous oscillation, harmonic generation, signal filtering and radiation. This leads to ultracompact THz circuits with low...
This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
Approximate computing is gaining increasing interest among the VLSI design community due to its potential for enabling low power, high speed, and less area while delivering acceptably correct computation results for many digital signal processing applications. In this context, this paper considers for the first time asynchronous quasi-delay-insensitive (QDI) realizations of approximate adders which...
A fully integrated low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end implemented in 180nm CMOS technology is demonstrated. The proposed double push-pull LNA collaborates with a current-mode down-converter to provide wideband low-noise reception, as well as the out-of-band blocker resilience. A sliding frequency synthesizer (FS) with low-frequency running VCO is employed to provide...
The paper presents a CMOS clock and data recovery (CDR) circuit for a full-rate 40 Gb/s optical receiver, and the proposed CDR adopts a mixer-based phase detector (MBPD). The MBPD approach offers several advantages such as capability to operate high frequencies, and a linear relationship between the phase difference and the output current. However, an MBPD requires a frequency-doubling mechanism (FDM)...
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