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Mobile communication and navigation devices have fueled the demand for low power implementations to enhance battery life. A critical aspect of reducing power in these devices is the efficiency of the process of converting power from the battery to the various loads in the system. This makes high-efficiency DC-DC switching power converters a natural candidate for such task. Unfortunately, however,...
Digital MIMO receivers featuring digitization at each element are critical for (massive) MIMO applications since they support complex space-time signal processing. However, the lack of spatial selectivity in the analog/RF domain necessitates high-dynamic-range analog-to-digital converters (A/Ds) to accommodate the uneven spatial power distribution, limiting the scale of such MIMO systems. This paper...
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also...
This paper proposes implementing an antenna operating in the millimeter wave band of 56–64 GHz on the backside of an Integrated Circuit (IC) that uses Through Silicon Via (TSV) technology for a System in Package (SiP) approach to mixed signal design. A folded monopole antenna that utilizes a coaxial TSV feed line is selected to implement the design on the backside of the silicon die. Furthermore,...
This paper presents an optical receiver (RX) suitable for amplifying a high-speed PAM-4 signal. To achieve a high gain-bandwidth product at low power consumption, a triple inductively peaked regulated cascode (RGC) transimpedance amplifier is used. The inductors are implemented as small 3D solenoids to reduce chip area and optimized for minimum group delay variation. The receiver further includes...
A scheme to achieve simultaneously extremely high slew rate improvement and avoiding open loop gain degradation in one stage super class-AB op-amps is introduced. It overcomes the serious shortcoming of super class-AB OTAs that show very high output current enhancement factors at the expense of degrading the open loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain...
In this paper, a time-mode resonator is presented that is used to realize a second-order bandpass ΔΣ time-to-digital converter (TDC). The resonator is constructed as a cascade of two lossless discrete-time integrators implemented using time-latches and some digital logic in a negative feedback configuration. This paper presents for the very first time the means in which time-mode circuits are used...
The paper presents a CMOS clock and data recovery (CDR) circuit for a full-rate 40 Gb/s optical receiver, and the proposed CDR adopts a mixer-based phase detector (MBPD). The MBPD approach offers several advantages such as capability to operate high frequencies, and a linear relationship between the phase difference and the output current. However, an MBPD requires a frequency-doubling mechanism (FDM)...
In this paper, a novel neural network architecture is proposed which results in an area-efficient feed-forward network. These structures require high-resolution multipliers. In order to overcome this problem, a mixed-signal Multiplying Digital to Analog Converter (MDAC) architecture which employs Delta-Sigma Modulation (DSM) to encode the multiplication results into the time domain. The time-domain...
Using a new DC offset compensation method, a fully differential track and hold circuit is presented. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip...
Data-state decision feedback equalizers (DFEs) suffer from a fundamental drawback of deteriorating vertical eye-opening when consecutive 1s or 0s are present in data. To combat this, a new data-transition adaptive DFE termed data-transition DFE is proposed. We show that data-transition DFE does not reduce vertical eye-opening whereas data-state DFE shrinks vertical eye-opening when consecutive 1s...
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