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LDPC codes have been applied in recent communication standards, such as WiFi, WiGig, and 10GBased-T Ethernet as a forward error correction code. However, LDPC codes require a large number of computational complexity for high performances. To solve this problem, various studies have been continuously performed for reducing computational complexity. In this paper, we propose an adaptive forced convergence...
Stochastic turbo decoder is a new scheme for turbo codes. But the long decoding latency and high complexity are two main challenges for fully parallel stochastic turbo decoders. In this paper, we proposed a novel stochastic turbo decoder scheme with two high accuracy stochastic operator modules, including no-scaling stochastic addition and stochastic normalization operator, which can improve the decoding...
Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the ‘worst-case’...
In this paper, a high speed digital excess loop delay (ELD) compensation scheme with hybrid thermometer coding is proposed. In this high speed compensation, the time constraint of the DAC feedback route is shifted to the one clock compensation path. Also, the method to deal with the signal overflows the quantizer's range is analyzed. Compared to other digital ELD compensations, this scheme features...
Internet of Things (loT) is network connected “Things” such as vehicles, buildings, embedded systems, sensors, as well as people. IoT enables these objects to collect and exchange data of interest to complete various tasks including patient health monitoring, environmental monitoring, system condition prognostics and prediction, smart grid, smart buildings, smart cities, and do on. Due to the large...
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
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