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A mixed-mode analog-digital transposed 64-tap finite impulse response filter for multi-channel biomedical monitoring systems is presented. The presented architecture conducts multiplication in analog domain by taking advantage of a compact preceding multiplying-ΔΣ ADC, which is implemented by reusing the in-channel current-mode stimulating DAC. The analog domain multiplication results in a ×16.4 saving...
A Look-Up Table (LUT) shows modest performance (delay and power) when used as a universal logic module (ULM) for implementing all possible combinational functions; moreover, the complete programmability of a LUT (so for all functions) incurs in a significant circuit complexity. Few approaches have been proposed by which a LUT is replaced by circuits; this is possible because in practice, the number...
We treat the design problem of second-degree IIR digital differentiators. The design problem (cost function) is formulated in the quadratic form without any frequency sampling. Since the cost function is the quadratic form, the solution is unique and the optimization scheme does not require any recursive optimization. Hence, the procedure of the design for the second-degree differentiators is very...
Low delay maximally flat in passband and equiripple in stopband (MFER) FIR Digital Differentiators (DDs) are known to have high differential accuracy with low delay. The transfer function is defined as the subtraction of the stopband function from the passband function. The passband function and the stopband function realizes flatness characteristics and equiripple characteristics, respectively. However,...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
A serial-link repeater chip with a single stage continuous-time linear equalizer (CTLE) and a 3-tap feedforward equalizer (FFE) is realized in a 0.13μm SiGe BiCMOS technology. The CTLE with the negative capacitance circuits is implemented to achieve a larger high-frequency boosting at the receiver side. By utilizing the LC-based delay elements, the FFE accomplishes the transmitter de-emphasis without...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state...
An alternative architecture to conventional voltage controlled oscillator based analog-to-digital converters (VCO-ADCs) is proposed in this paper. The new architecture allows to enhance the resolution of the converter without the need of extending noise shaping order. Instead, the oversampling ratio is increased by sampling the outputs of the VCO through an array of digital delay lines. The output...
This paper proposes a novel architecture for purely voltage controlled oscillator (VCO) based continuous-time (CT) second-order ΔΣ analog-to-digital converter (ADC) without using bulky, passive components. The proposed technique does not require any VCO nonlinearity calibration and is robust against excess loop delay and static and dynamic errors in the multi-element digital-to-analog converter (DAC)...
Memristor technology is receiving an increased attention as a potential solution to meet the scaling demands in integrated circuit design. Memristor provides advantages like high-density, low-power, non-volatility and good scalability. In this paper, an 8-bit iterative full adder design is proposed that uses space-time based circuit notation. It uses stateful logic with memristive nanowire crossbar...
Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the ‘worst-case’...
In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout...
In this paper, we propose a cross-layer integrated microprocessor design methodology where instructions in software programs drive the design down to the gate level netlists. Based on in-depth exploration of the dynamic timing behavior of each instruction in the program, a fully integrated design approach is proposed with ultra-dynamic clock and power management circuits and software driven design...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
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