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This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also...
Lattice-based cryptography has been widely researched due to its quantum attack resistance and versatility, but a practical hardware implementation that is suitable for constrained devices is still challenging. In this paper, a novel area-optimized Ring-LWE (Learning with Error) cryptographic processor is proposed. Effective structures are presented to solve the huge circuit consumption of high precision...
Internet of Things (loT) is network connected “Things” such as vehicles, buildings, embedded systems, sensors, as well as people. IoT enables these objects to collect and exchange data of interest to complete various tasks including patient health monitoring, environmental monitoring, system condition prognostics and prediction, smart grid, smart buildings, smart cities, and do on. Due to the large...
This work presents security solutions related to multi-sensor closed-loop artificial pancreas (AP) systems. The proposed AP system is built on a heterogeneous platform incorporating a smartphone, activity sensors, a glucose monitor, an insulin pump, a laptop hosting the multi-variable control algorithm and a cloud server. Developing a secure AP system is essential for mass adoption among diabetes...
In-Memory computing has drawn many attentions as a promising solution to reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency. Emerging spintronic device based non-volatile memory is becoming a next-generation universal memory candidate due to its non-volatility, zero leakage power in un-accessed...
This paper explores the use of On-chip cryptographic units for implementing security in low cost wireless sensor networks. The objective of this research is to reduce the deployment time and computational complexity of security protocols in WSNs, whilst keeping security related performance parameters at par with the current state-of-the-art. A method is proposed to continue using simple radio transreceiver...
Side-channel attacks against field-programmable gate arrays (FPGAs) enable attackers to reverse-engineer bitfile encryption keys, resulting in intellectual-property (IP) theft and tampering. To address this problem, we demonstrate that overlays — virtual architectures implemented atop an FPGA — provide a novel countermeasure strategy that can protect application IP even on vulnerable FPGAs. Although...
In most power analysis attack, power traces obtained from the cryptographic device are aligned using a crypto device based triggering signal. In reality, the attacker does not have the luxury of inserting a trigger in the encryption device source code. This paper aims to execute a CPA attack on an 8 bit PIC-microcontroller (μC) implementation of AES-128 encryption without a crypto μC-based triggering...
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