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In this work, we investigate the hardware implementation of Support Vector Machine (SVM) prediction on an FPGA platform for industrial ultrasound applications. Specifically, SVM is used as classifier for identifying ultrasonic A-scan signals as signals with flaw or signals without flaw. Hardware acceleration using FPGA is the main theme of the presented work. The architecture used to implement the...
As a popular deep learning technique, convolutional neural network has been widely used in many tasks such as image classification and object recognition. Convolutional neural network exploits spatial correlations in the images by performing convolution operations in local receptive fields. Convolutional neural networks are preferred over fully connected neural networks because they have fewer weights...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
Hardware implementations of Object-Tracking Algorithms, like most integrated circuits, are susceptible to radiation-induced soft errors. This work evaluated the reliability of a field-programmable gate array (FPGA) prototype for object-tracking algorithms via fault emulation experiments conducted at the register-transfer level (RTL). Faults were injected into the main sub-modules within the object-tracking...
This paper presents an original and unique embedded FFT hardware algorithm development process based on a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in a Kronecker Pease FFT hardware implementation. This is coupled by a procedure to perform automatic code generation of Kronecker FFT cores. The...
Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware...
Random number generators (RNGs) are an integral component of numerous stochastic simulation methods, with applications in diverse scientific disciplines. Recently, stochastic simulation methods are being increasingly implemented on FPGAs for improved performance. Consequently, efficient RNG implementations are essential to successfully realize stochastic simulation methods on FPGAs. We present a memory...
Scalar addition and multiplication generally obey commutative and distributive laws. However, in their hardware implementation, error propagation and accumulation do not necessarily follow the same rules. In this paper we present a statistical analysis of the accuracy in complex multiplication approaches for IEEE 754 single precision operands. Several approaches were evaluated using a dual approach...
The need for large primes in major cryptographic algorithms has stirred interest in methods for prime generation. Recently, to improve confidence and security, prime number generation in hardware is being considered as an alternative to software. Due to time complexity and hardware implementation issues, probabilistic primality tests are generally preferred. The Baillie-PSW primality test is a strong...
As genomic medicine becomes part of standard clinical care, Precision Medicine faces a daunting computational challenge in scaling up to support the genomic, image processing and analytics workloads required for millions of patients, especially in oncology clinics. Computational solutions based on heterogeneous hardware platforms like FPGAs have the potential to enable rollout of personalized care...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
Silicon based Physical Unclonable Function (SPUF), a chip level identifier that utilizes the inherent irregular manufacturing process variations, can be extended to Ring Oscillator PUFs (ROPUFs). The ROPUF structure, although promising for FPGA based platforms, is not area efficient in terms of response bit per RO circuit implementation. This paper introduces an area efficient Stage Configurable ROPUF...
Internet of Things (loT) is network connected “Things” such as vehicles, buildings, embedded systems, sensors, as well as people. IoT enables these objects to collect and exchange data of interest to complete various tasks including patient health monitoring, environmental monitoring, system condition prognostics and prediction, smart grid, smart buildings, smart cities, and do on. Due to the large...
This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array...
In this paper a random number generation method based on a piecewise linear one dimensional (PL1D) discrete time chaotic maps is proposed for applications in cryptography and steganography. Appropriate parameters are determined by examining the distribution of underlying chaotic signal and random number generator (RNG) is numerically verified by four fundamental statistical test of FIPS 140-2. Proposed...
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data...
Side-channel attacks against field-programmable gate arrays (FPGAs) enable attackers to reverse-engineer bitfile encryption keys, resulting in intellectual-property (IP) theft and tampering. To address this problem, we demonstrate that overlays — virtual architectures implemented atop an FPGA — provide a novel countermeasure strategy that can protect application IP even on vulnerable FPGAs. Although...
This paper proposes a hardware architecture of the multi-band spectral subtraction method for real-time speech enhancement. The proposed hardware architecture has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG) and Nexys-4 development board. Multi-band approach is based on the fact the whole speech spectrum does not be affected uniformly by the colored...
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