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This paper investigates a class of electrical generators based on capacitors and diodes, with two capacitors being variable. Their main characteristics are a symmetrical structure and that they produce two outputs with the same polarity. The simplest version is analyzed in more detail, although in an approximate way, and generalizations of it are obtained, identified with a particular form of two-phase...
This paper proposes a new strategy for vibration harvesting using piezoelectric material. This work relies on an adaptation of the classical Synchronous Electrical Charge Extraction (SECE). Instead of harvesting the energy at every displacement extremum, we choose to wait a certain number of extremum before harvesting the accumulated energy. This technique extends the harvested power compared to SECE,...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
This paper presents an adaptive edge decision feedback equalizer (DFE) with 4PAM signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are obtained adaptively using sign-sign least-mean-square (SS-LMS) algorithms that minimize data jitter. Clock and data recovery is carried out using a dual phase/frequency-locked loop. A 10 Gbps 4PAM serial link has been designed in a 65...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array...
True Random Number Generators (TRNG) are used in a variety of applications including cryptographic algorithms, communication systems, simulations, etc. From a security perspective, TRNGs are particularly important because they can produce random output bits that are fully unpredictable and unbiased. Random sources are not often apparent and it is useful to have intrinsic hardware-based random number...
This paper introduces a 401–457 MHz BFSK transmitter (TX) architecture that utilizes mixing and image rejection techniques to generate the two carrier frequencies for BFSK transmission. The proposed architecture enables low power consumption for a wide range of data rates by avoiding fast settling time requirements for the frequency-locked loop. Simulations indicate that the TX designed in 130nm CMOS...
This paper proposes a hardware architecture of the multi-band spectral subtraction method for real-time speech enhancement. The proposed hardware architecture has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG) and Nexys-4 development board. Multi-band approach is based on the fact the whole speech spectrum does not be affected uniformly by the colored...
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