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A Look-Up Table (LUT) shows modest performance (delay and power) when used as a universal logic module (ULM) for implementing all possible combinational functions; moreover, the complete programmability of a LUT (so for all functions) incurs in a significant circuit complexity. Few approaches have been proposed by which a LUT is replaced by circuits; this is possible because in practice, the number...
In this paper, an X-tree clock distribution topology based on standing wave oscillator is introduced. To increase output amplitude at the loading point and saving chip area, a novel CMOS active inductor is designed and applied to each loading points of the network. The cascoded differential active inductor is 1 nH with Q = 344 at 10 GHz. This makes the two stage, 6.2 mm × 6.2 mm dimensional standing...
Pioneering developments in electrical engineering are based on inspirations from biology. They exhibit naturally an efficient information processing. For example, hardware realizations of memristive circuits mimicking the anticipatory behavior of unicellular organisms like amoebas have been developed in this context. Unfortunately, circuits are not appropriate for algorithms dedicated in the area...
Neuromorphic circuits are potential candidates for solving costly computations in an efficient manner. Such circuits, mimicking partial functionalities of the brain, need a large number of components. Simulation models are appropriate for first investigations, but they are very time-consuming regarding complex systems. Hardware realizations of specific components, like memristive devices, in such...
Selfdischarge characteristics of supercapacitors play a significant role in their sizing and power management. Furthermore, supercapacitor-s' selfdischarge, defined as no load voltage drop, is directly proportional to its charging rate. The paper proposes a framework to empirically model the terminal voltage response of supercapacitors during charge and selfdischarge. A set of empirical formulae has...
Sedimentary microbial fuel cells are promising harvesting systems generating powers as low as 10 μW, which is sufficient for powering underwater environmental sensors. This paper proposes a methodology and modeling to design a flyback converter in discontinuous conduction mode harvesting powers as low as 10th of μWs to maximize the harvested energy and boost its voltage to a minimum value required...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
A spiking neuron and 3-terminal Resistive RAM (RRAM) model are proposed and simulated as a neural network. The system is analyzed as a complex network of spiking neurons connected by synapses to demonstrate a biologically-inspired associative memory. In recent years, Machine Learning and Artificial Intelligence have become popular fields due to readily available high performance computing systems...
In this paper, we illustrate, through examples, a novel graph-based modeling technique of two-state (on-off) PWM power converters. Differential equations of power converters are derived by inspection, based on two incident matrices, β(u) and J(u). We associate to each circuit (on, u = 1, or off, u = 0, circuits) a digraph and identify current loops (inductor-capacitor, voltage source-inductor, current...
Simulation of complex hardware circuits is the basis for many EDA tasks and is commonly used at various phases of the design flow. State-of-the-art simulation tools are based upon discrete event simulation algorithms and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common...
A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking protocol. Thus, we model gates as transition systems and provide correctness property templates that capture safety and liveness. The methodology is demonstrated using several circuits.
This paper provides a proof-of-concept demonstration of the potential benefit of using logical implications for detection of combinational hardware trojans. Using logic simulation, valid logic implications are selected and added to to the checker circuitry to detect payload delivery by a combinational hardware trojan. Using combinational circuits from the ISCAS benchmark suite, and a modest hardware...
This paper presents a new approach towards the design and implementation of high-throughput impedimetric screening for life science applications. Herein, we propose a new cell-on-chip model for cellular analysis. A low complexity platform was developed to demonstrate the advantages of this model for cellular analysis. This low cost platform consists of an array of optically transparent electrodes...
This paper is on the study of double coupled oscillators, where two cross-coupled differential oscillators share the same bias current. Without external coupling, competition for bias current happens, and the one with a higher Q can grab most of the current, and the other one is starved to death. With external coupling, a beat pattern is generated and the beat frequency is strongly related to the...
Memelements — circuit elements with memory — serve novel applications in several technical disciplines. Due to similar functionalities to synapses, they are especially suitable for neuromorphic circuits. Physical and chemical phenomena in the nano-scale lead to the unique information storage characteristic of these elements. Fabrication of devices with memory considering a particular desired functionality...
The equivalent circuit model parameters of the barrel-stave flextensional transducer and array are calculated using the circuit principle together with the finite element, boundary element method and the measured results. The electro-acoustic characteristics of the transducers and arrays are analyzed by the obtained equivalent circuit model. The resonant frequencies and admittance curves of the transducers...
In this paper, we present artificial neural network (ANN) models to predict hard and soft-responses of three configurations of arbiter based physical unclonable functions (PUFs): standard, feed-forward (FF) and modified feed-forward (MFF). The models are trained using data extracted from 32-stage arbiter PUF circuits fabricated using IBM 32 nm HKMG process. The contributions of this paper are two-fold...
Spin based memories have garnered major interest in recent times. With all of the alluring features like-non-volatility, zero-stand by leakage and dense integration in array, they suffer from not having satisfactory distinguishability between stored memory states. Recently, a novel approach of using Phase transition materials (PTM) to assist magnetic tunnel junction (MTJ) in spin memories has been...
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking...
A CMOS synapse design is presented which can perform tunable asymmetric spike timing-dependent learning in asynchronous spiking neural networks. The overall design consists of three primary subcircuit blocks, and the operation of each is described. Pair-based Spike Timing-Dependent Plasticity (STDP) of the entire synapse is then demonstrated through simulation using the Cadence Virtuoso platform....
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