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This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
The Sun has the potential to provide 89,300 tera Watts of power to our planet. Our ability to convert even a fraction of this energy for human use makes a significant impact on current energy generation and consumption trends. World-wide we now add more renewable energy capacity every year than (combined) fossil fuel energy capacity. Solar panels provide a reliable, renewable, non-polluting energy...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
An alternative architecture to conventional voltage controlled oscillator based analog-to-digital converters (VCO-ADCs) is proposed in this paper. The new architecture allows to enhance the resolution of the converter without the need of extending noise shaping order. Instead, the oversampling ratio is increased by sampling the outputs of the VCO through an array of digital delay lines. The output...
Locally NOR and globally NAND match-line architecture and sensing circuits applicable to the high performance content addressable memory(CAM) is proposed in this paper. As word-length of CAM gets longer, the capacitance of match-line gets larger and it causes performance degradation and large dynamic power consumption. Local match-lines are segments of large capacitive match-line and designed as NOR-type...
This paper discusses an analytical method for performance estimation of multi-stage transimpedance amplifier (TIA). For high speed and energy efficient optical communication, multi-stage TIA composed of pre-amplifier (PA) and Cherry-Hooper amplifier (CHA) are commonly used. However, it is not clear how to decide design parameters of PA and CHA. Additionally, the number of stages is also a design parameter...
In conventional design of Nauta transconductor, the limitation of output voltage swing is usually the price for very high DC-gain due to inevitable non-linear effects in the transconductor. Nevertheless, a new design of Nauta transconductor in sub-micron CMOS technology with digitally-controlled transconductance may bring along opportunities to adjust the intrinsic gain of Nauta transconductor which,...
This paper presents the design for a dc circuit breaker based on the coupled-inductor for use in dc grid protection. The breaker acts autonomously as a result of the fault current path. The exact step change in current required to open the breaker can be adjusted in the design by selecting an appropriate turns ratio for the coupled-inductor. A simulation is run for a zonal dc grid to demonstrate the...
Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS...
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