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A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
Intravascular ultrasonic (IVUS) imaging catheters currently use ceramic piezoelectric transducers to form radial images of blood vessel walls. Further improvements in image quality may be enabled through Capacitive and Piezoelectric Micromachined Ultrasonic Transducers (CMUTs and PMUTs). Polymer PMUTs offer many benefits in imaging quality, however, the low acoustic sensitivity and high electrical...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
In this paper, an advanced layout scheme of an integrated capacitor is presented which improves the efficiency of a poly-poly capacitor based voltage doubler charge pump. The main losses in voltage doubler charge pumps are mathematically described and the importance of low stray capacitances are discussed. By means of the improved poly-poly capacitor layout, the usable capacitance is increased while...
In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout...
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking...
Gradient errors in device arrays cause mismatch between device parameters, which in turn degrade linearity performance of data converters realized with these arrays. A practical “outputs averaging” technique for string DACs is presented to release complex routing problems in gradient reduction patterns. An N-bit string is divided into multiple substrings and the substrings' outputs are averaged to...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only...
An aggressive controlling for layout pattern density is becoming essential for the manufacturability of advanced processes. Focusing on analog layout under severe density constraints, this paper provides a novel idea that layout generation and verification are co-working on a density-aware format. Our idea follows a transistor-array(TA)-style of analog layout where unit-transistors of the same channel-size...
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