The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a CMOS image sensor with high conversion-gain pixels and column-shared pipelined ADCs for Fluorescence-lifetime imaging microscopy (FLIM). Pixel conversion gain of 121 uV/e-is achieved by creating a distal floating diffusion from transfer gate and reset transistor gate without any process modification. 32-channel 10-bit on-chip column-shared pipelined ADCs with sampling rate up...
Novel ultra-compact sub-10nm XOR, NOR and NAND CMOS logic circuits based on ambipolar characteristics of Schottky-Barrier (SB) FinFET devices and gate metal workfunction engineering are introduced. Use of SB source and drain contacts, high-k gate dielectrics and ultra-thin body bestows extreme short-channel immunity to the proposed FinFETs with ambipolar current-voltage characteristics. Thus, the...
This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
A spiking neuron and 3-terminal Resistive RAM (RRAM) model are proposed and simulated as a neural network. The system is analyzed as a complex network of spiking neurons connected by synapses to demonstrate a biologically-inspired associative memory. In recent years, Machine Learning and Artificial Intelligence have become popular fields due to readily available high performance computing systems...
Simulation of complex hardware circuits is the basis for many EDA tasks and is commonly used at various phases of the design flow. State-of-the-art simulation tools are based upon discrete event simulation algorithms and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common...
A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking protocol. Thus, we model gates as transition systems and provide correctness property templates that capture safety and liveness. The methodology is demonstrated using several circuits.
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
Outsourcing designs to 3rd party vendors is a common practice in the integrated circuit (IC) manufacturing industry. This outsourcing brings advantages such as lower manufacturing cost and shorter time-to-market for a new system, which at the same time raises security threats in the IPs from 3rd party vendors. These IPs may contain hardware Trojans capable of compromising the product's confidentiality,...
This paper provides a proof-of-concept demonstration of the potential benefit of using logical implications for detection of combinational hardware trojans. Using logic simulation, valid logic implications are selected and added to to the checker circuitry to detect payload delivery by a combinational hardware trojan. Using combinational circuits from the ISCAS benchmark suite, and a modest hardware...
This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state...
The advancing trend to autonomous driving tightens the requirements for automotive microcontrollers with embedded flash memories. High reliability and low latency demands however have prevented the broad usage of multilevel-cell flash in this sector so far. This paper describes a robust time-domain voltage sensing scheme tackling the challenges arising from these tight conditions. A dynamic voltage...
Memristor technology is receiving an increased attention as a potential solution to meet the scaling demands in integrated circuit design. Memristor provides advantages like high-density, low-power, non-volatility and good scalability. In this paper, an 8-bit iterative full adder design is proposed that uses space-time based circuit notation. It uses stateful logic with memristive nanowire crossbar...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
A CMOS Crystal Oscillator with automatic amplitude control (AAC) is presented which occupies low area and consumes lower current when compared to existing state of the art designs. Amplitude control loop based implementations of low frequency crystal oscillators usually achieve low-power operation at the expense of die area. The proposed design aims at reducing the overall area by replacing the bulky...
The paper describes evaluation of the first, second and (with most attention to) third harmonics of the drain current in a MOS transistor operating in moderate inversion. The dependence of this current on the gate-source voltage is approximated using a simplified “reconciliation” model developed by Y. Tsividis. Then, the drain current components depending exponentially on normalized signal voltage...
This paper proposes a novel fully differential ultra-low voltage transimpedance amplifier (TIA) based on a CMOS translinear circuit. Following a simple bias strategy, its transimpedance gain can be adjusted to the desired accuracy either by means of an external resistor or using internal voltage and current references. To a first order approach, the transresistance results independent from technological...
This paper discusses an analytical method for performance estimation of multi-stage transimpedance amplifier (TIA). For high speed and energy efficient optical communication, multi-stage TIA composed of pre-amplifier (PA) and Cherry-Hooper amplifier (CHA) are commonly used. However, it is not clear how to decide design parameters of PA and CHA. Additionally, the number of stages is also a design parameter...
A scheme to achieve simultaneously extremely high slew rate improvement and avoiding open loop gain degradation in one stage super class-AB op-amps is introduced. It overcomes the serious shortcoming of super class-AB OTAs that show very high output current enhancement factors at the expense of degrading the open loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain...
Due to the globalized semiconductor supply chain, integrated circuits suffer from hardware security attacks. Among various attacks, hardware Trojan insertions have emerged as a major security concern. An adversary modifies the original circuit to accomplish the malicious intentions through the hardware Trojan. Hardware obfuscation has been demonstrated as a promising technique to strengthen hardware...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.