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We propose μLeech, a new embedded trusted platform module for next generation power scavenging devices. Such power scavenging devices are already widely deployed. For instance, the Square point-of-sale reader uses the microphone/speaker interface of a smartphone for communications and as power supply. While such devices are used as trusted devices in security critical applications in the wild, they...
Efficient and smart techniques for analog data acquisition and processing may play crucial role in the design of miniature wearable devices, meant to continuously record, process and wirelessly transmit vital physiological parameters for real time health monitoring. In this work we propose a low-power, all-analog processing unit for an MPG (magneto-plethysmograph) based wearable device, which is meant...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
A 7GS/s 6b sub-ranging ADC is implemented in 32nm CMOS SOI with reconfigurable comparators, and adjustable input differential pairs are exploited to change converter characteristics for hardware-based cybersecurity. To achieve low-power consumption at high-speed operation with small-size transistors, an on-chip calibration to reduce process mismatches is utilized in the design. The presented ADC achieves...
We present the design and implementation of a monolithic microwatt analog front end and asynchronous level-crossing ADC for efficient capture of sparse biopotentials. The low-noise differential AC-coupled front-end provides +40 dB gain, and the signal is digitized by an asynchronous level-crossing ADC which encodes the signal slope into a stream of pulses. For temporally-sparse signals such as single-unit...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
A passive delta-sigma ADC with a voltage-controlled-oscillator (VCO) quantizer is presented. By employing the VCO quantizer, a single-bit quantizer is replaced with a multi-bit quantizer while an extra order of noise-shaping was provided. The proposed architecture does not need very large capacitors as compared to the conventional passive delta-sigma ADC. Furthermore, it also does not require external...
A scheme to achieve simultaneously extremely high slew rate improvement and avoiding open loop gain degradation in one stage super class-AB op-amps is introduced. It overcomes the serious shortcoming of super class-AB OTAs that show very high output current enhancement factors at the expense of degrading the open loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain...
Fall has become a serious medical problem, and sometimes leading to physical disabilities and death. This led researchers to pursue automatic monitoring systems for detecting the falls before they occur. Much of the existing efforts have successfully achieved a hardware system which provides a fall pattern after and prior to the fall. However, the existing fall detection systems are still deficient...
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