The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced....
The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable Nonvolatile memory (NVM) component is STT-MRAM. There is a demand to improve efficient circuit and architecture to compete with the existing NVM technologies. Low energy consumption is achieved to write and read into MTJ. This...
Photovoltaics continue to be the primary source of electrical power for most near-Sun space missions. The desire to enhance or enable new space missions through higher efficiency, increased specific power density, increased volumetric power density and improved radiation resistance, along with decreased costs, continues to push the development of novel solar cell and array technologies. To meet present...
This paper describes a direct coupled neural amplifier with active electrode offset suppression in order to avoid large coupling capacitors and complex chopper circuits. It describes a novel feedback scheme, where a low pass current mode feedback is applied to a regulated telescopic cascode amplifer, at the cascode nodes by using a modified transconductance block. This solution leads to fully differential...
The genetic engineering of microbial organisms offers benefits to society through biotechnology applications. Traditionally, the “engineering” of microbes to arrive at organisms with desired behavior has not been engineering in a strict sense. It has, rather, required months (more often years) of trial-and-error type of experiments, with the undertaking being more akin to art than engineering. Enter...
This paper presents a new framework for the design optimization of a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The framework exploits the gm/ID methodology to find the transistors' dimensions that optimize the tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the mixer. The mixer has been designed using a 0.13 μm...
The standard LSTM recurrent neural networks while very powerful in long-range dependency sequence applications have highly complex structure and relatively large (adaptive) parameters. In this work, we present empirical comparison between the standard LSTM recurrent neural network architecture and three new parameter-reduced variants obtained by eliminating combinations of the input signal, bias,...
Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.