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This paper focuses on the design and analysis of multi-stage noise-shaping (MASH) sigma-delta modulators. Fundamentals and properties of MASH modulators are discussed. A detailed methodology on analyzing continuous-time MASH (CT-MASH) modulator based on the impulse invariant transformation is also described. Two fabricated design examples are discussed: a 130 nm CMOS CT-MASH 4-0 employing a digital...
A novel multi-dimensional noise-shaping method is proposed to extend Δ-Σ modulation to the two-dimensional (2-D) (space, time) case. It uses spatial oversampling to provide another degree of freedom for ADC designers to shape quantization noise when temporal oversampling is limited. The method uses lossless discrete integrators (LDIs) to implement spatial integrators and is suitable for use in microwave...
This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state...
This paper proposes a novel architecture for purely voltage controlled oscillator (VCO) based continuous-time (CT) second-order ΔΣ analog-to-digital converter (ADC) without using bulky, passive components. The proposed technique does not require any VCO nonlinearity calibration and is robust against excess loop delay and static and dynamic errors in the multi-element digital-to-analog converter (DAC)...
A passive delta-sigma ADC with a voltage-controlled-oscillator (VCO) quantizer is presented. By employing the VCO quantizer, a single-bit quantizer is replaced with a multi-bit quantizer while an extra order of noise-shaping was provided. The proposed architecture does not need very large capacitors as compared to the conventional passive delta-sigma ADC. Furthermore, it also does not require external...
Analog to digital converters (ADC) are used in wireless receivers to process signals in the presence of blockers. These blockers, usually much larger than the signal itself, necessitate the use of a filter upfront to reduce the dynamic range requirement of the ADC. A filtering ADC can be created by placing both the filter and the ADC in a global feedback loop, with improvement in noise and power efficiency...
In this paper, a high speed digital excess loop delay (ELD) compensation scheme with hybrid thermometer coding is proposed. In this high speed compensation, the time constraint of the DAC feedback route is shifted to the one clock compensation path. Also, the method to deal with the signal overflows the quantizer's range is analyzed. Compared to other digital ELD compensations, this scheme features...
This paper introduces a speed-enhanced incremental ADC architecture for high-resolution low-power sensor applications, incorporating a third-order sturdy MASH modulator. Unlike previous sturdy MASH ADCs, owing to the properly modified loop filters in the 2-1 sturdy MASH, the quantization noise of the first noise-shaping loop could be cancelled out. The proposed ADC with a 4b coarse SAR ADC and a 2-1...
In this paper it will be shown that propagating specific state registers in a fully parallel Delta-Sigma Architecture can have a profound impact in enhancing the performance of these type of modulators without stringent requirements in terms of latency and resources usage. An FPGA-based transmitter was implemented and designed to validate the proposed architecture, and to demonstrate that flexible,...
This paper presents a quantitative evaluation of the power efficiency decrease obtained by breaking the zero-current switching (ZCS) condition due to the alternate output occurring in a bi-level quadrature-modulation (QM) envelope-pulse-width-modulation (EPWM) transmitter. The power efficiency is evaluated by changing the Q factor of the series resonance circuit inserted in a power amplifier (PA)...
The requirements for data conversion in CMOS Image Sensors are increasing due to number and size of pixels and can not be met anymore by classic ramp converters. To address this issue, this paper presents a compact 14-bit two-stage Incremental-ΣΔ column-parallel ADC for use in CMOS Image Sensors. The ADC as well as a test array for a pixel matrix has been fabricated in a 110nm optical CMOS process...
Two Band-Pass (BP) Discrete Time (DT) ΔΣ modulators are proposed in this paper. In both cases, the drawback of high-speed power-hungry adder is tackled by proposing a modified unity signal transfer function (STF) adder-less feedforward structure. The first proposed BP DT ΔΣ modulator is a conventional adder-less multi-stage noise shaping (MASH) ΔΣ modulator, while the noise leakage problem, caused...
In this paper, a time-mode resonator is presented that is used to realize a second-order bandpass ΔΣ time-to-digital converter (TDC). The resonator is constructed as a cascade of two lossless discrete-time integrators implemented using time-latches and some digital logic in a negative feedback configuration. This paper presents for the very first time the means in which time-mode circuits are used...
In this paper, we explain the THz detection mechanism in sub-threshold Si MOSFETs by exploiting the exponential dependence of channel electron density to the gate-source voltage. According to our theory, this high frequency non-linear dependence is the underlying mechanism for rectification of THz radiation. The maximum detection frequency is limited by dielectric relaxation time of the electrons...
Pseudo-differential circuits approximate the performance of fully-differential structures, while allowing single-ended operation of the two half stages in the circuit. This requires duplication of the circuitry, with accurate symmetry needed between the two halves to cancel common-mode noise. This paper proposes a single-ended scheme which uses double sampling and time interleaving to achieve a performance...
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