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This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
This paper presents a method for calculating the semiconductor losses in asynchronous and synchronous PWM buck converters when operated as a fixed-VI, fixed-RL, variable-Vo dynamic power supply. Equations are derived for MOSFET switching and conduction losses in both circuits, as well as diode conduction and forward-voltage losses. This work also compares the two topologies from the perspective of...
In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation,...
We present performance characterization of a bio-potential recording system with an asynchronous readout architecture. The signal processing chain consists of a low-noise bio-potential amplifier, spike detection circuitry, and an address event representation (AER) communication protocol. The system was fabricated in a 0.5 pm CMOS technology. Each stage of the recording system was tested individually,...
The paper describes evaluation of the first, second and (with most attention to) third harmonics of the drain current in a MOS transistor operating in moderate inversion. The dependence of this current on the gate-source voltage is approximated using a simplified “reconciliation” model developed by Y. Tsividis. Then, the drain current components depending exponentially on normalized signal voltage...
A fourth-order Butterworth active Gm-C complex IF filter for dual-mode GNSS receiver is presented. This filter operates at center frequency of 7.161MHz and in bandwidth of 4MHz with pass-band gain of over 10dB and image rejection of over 35dB, which meets requirements of BD2 and Galileo Systems. The proposed CMOS fully differential transconductor has wide tuning range, high linearity and low power...
In this paper we present a systematic method to synthesize and analyze fully differential input-output filters using two port networks. Transfer functions, input and output impedance can be evaluated for various impedances and transmission matrices varied to investigate the filter's performance. Experimental and simulated results in Cadence are provided.
This paper presents a static non-linearity correction technique exemplary applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in 180 nm CMOS. The proposed technique proves for the first time, that an undesired power supply and package resistance can be turned into a benefit by canceling non-linearity effects introduced by the MOSFET switches within the source...
This paper presents a new framework for the design optimization of a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The framework exploits the gm/ID methodology to find the transistors' dimensions that optimize the tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the mixer. The mixer has been designed using a 0.13 μm...
Memristor is considered as one of the promising solutions to the fundamental limitations of the VLSI systems. Logic implementation with memristor device by considering its compatibility with CMOS fabric provides a new vision for digital logic circuits. This work presents a 2 by 2 multiplier cell design using a hybrid CMOS-memristor universal gate. The universal gate based implementation approach is...
In this paper, we explain the THz detection mechanism in sub-threshold Si MOSFETs by exploiting the exponential dependence of channel electron density to the gate-source voltage. According to our theory, this high frequency non-linear dependence is the underlying mechanism for rectification of THz radiation. The maximum detection frequency is limited by dielectric relaxation time of the electrons...
This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only...
An aggressive controlling for layout pattern density is becoming essential for the manufacturability of advanced processes. Focusing on analog layout under severe density constraints, this paper provides a novel idea that layout generation and verification are co-working on a density-aware format. Our idea follows a transistor-array(TA)-style of analog layout where unit-transistors of the same channel-size...
Numerator of the voltage gain transfer functions is directly derived with Trajectance analysis in this paper. Denominator of the voltage gain transfer functions is directly calculated by Suspendance analysis that was explained in prior publications. The voltage gain numerator is obtained by i) identifying all paths that connect the input node to output node of the circuit through sequential passive...
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