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Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel...
A mixed-mode analog-digital transposed 64-tap finite impulse response filter for multi-channel biomedical monitoring systems is presented. The presented architecture conducts multiplication in analog domain by taking advantage of a compact preceding multiplying-ΔΣ ADC, which is implemented by reusing the in-channel current-mode stimulating DAC. The analog domain multiplication results in a ×16.4 saving...
This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also...
In this paper, an low power CMOS temperature sensor for implantable applications is implemented in a 0.18 μm CMOS process. Sensors for implantable devices must have sub-μW power consumption to avoid tissue overheating. Thus, this temperature sensor employs subthreshold MOS transistors as the sensing element to reduce power consumption and enable minimum supply voltage. Temperature is converted to...
Wireless transceivers that receive data and power are important circuit blocks in implantable biomedical devices. In such wirelessly powered devices, supply and common-mode variations increase the error rate of the received data. In this paper we propose a fully-differential amplitude-shift-keying (ASK) demodulator for suppressing the effect of such undesired common mode variations on the received...
The ever-increasing need for higher number of neural recording channels along with the stringent power and area requirements of a brain-implantable device, demand for ultra-compact and scalable channel architectures. In this paper, we will first briefly discuss the fundamental scaling issues of conventional AC- and DC-coupled neural front-ends. Next, we will analytically examine the feasibility of...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
In this paper, effects of amplifier distortion in DT sigma-delta modulator are discussed. A second order modulator with single-bit quantizer is modeled and dead-zone effect of ring amplifiers in integrators is simulated by using MATLAB. For the evaluation of dead-zone effect on modulator distortion, test chip was fabricated in 65nm CMOS. SNDR of 62dB and 1MHz signal bandwidth was experimentally demonstrated...
We present the design and implementation of a monolithic microwatt analog front end and asynchronous level-crossing ADC for efficient capture of sparse biopotentials. The low-noise differential AC-coupled front-end provides +40 dB gain, and the signal is digitized by an asynchronous level-crossing ADC which encodes the signal slope into a stream of pulses. For temporally-sparse signals such as single-unit...
Locally NOR and globally NAND match-line architecture and sensing circuits applicable to the high performance content addressable memory(CAM) is proposed in this paper. As word-length of CAM gets longer, the capacitance of match-line gets larger and it causes performance degradation and large dynamic power consumption. Local match-lines are segments of large capacitive match-line and designed as NOR-type...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
Low-dropout voltage regulators (LDOs) have been extensively used on-chip to supply voltage for various circuit blocks. Digital LDOs (DLDO) have recently attracted circuit designers for their low voltage operating capability and load current scalability. Existing DLDO techniques suffer from either poor transient performance due to slow digital control loop or poor DC load regulation due to low loop...
In this paper a novel wideband transformer-based CMOS VCO with simplified topology and digital amplitude calibration is proposed. Owing to the digital amplitude calibration, the immunity to process, temperature and voltage supply variations is improved and a considerable reduction of power consumption is observed (i.e. over 25% in normal process corner, supply voltage and temperature). Besides, the...
Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. In this work, we propose a new cache architecture, called Janus, to enable crypto-systems to introduce randomization and uncertainty in their runtime timing behavior...
A signal conditioning circuit with ultra-high sensitivity and ultra-low power consumption is presented for the capacitive and voltage mode microelectromechanical systems (MEMS) transducers. Two different amplifiers are chopped with two different frequencies to remove their flicker noise. A low voltage high current amplifier is implemented in the 1st stage, which improves the power consumption and...
This paper presents a lossless sensor data compression accelerator for power reduction in wireless body sensors. First, a low complexity compression algorithm is demonstrated for the first time on electrocardiogram (ECG) and acceleration sensor data. Second, the algorithm is implemented as a custom hardware accelerator on a health monitoring driven System on Chip (SoC) in a 130 nm process. The accelerator...
A highly linear bridge-based constant voltage and constant current ISFET pH sensor readout circuit is proposed. In this scheme, a compact and low power pH sensor readout circuit is realized by using only one opamp and three MOSFETs without degrading the accuracy. The proposed circuit is implemented using standard CMOS 0.18 μm technology that shows chemical sensitivity of −37mV/pH, power consumption...
Emerging trend in neuromorphic implementation moves towards large-scale neuron array that processes large amount of input data. It presents a grand challenge in communication between neurons due to large number of connections, or synapses, which can be in the order of millions, leading to large power consumption, processing time and many physical wires. In this work, we propose a communication protocol...
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