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This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
Hardware implementations of Object-Tracking Algorithms, like most integrated circuits, are susceptible to radiation-induced soft errors. This work evaluated the reliability of a field-programmable gate array (FPGA) prototype for object-tracking algorithms via fault emulation experiments conducted at the register-transfer level (RTL). Faults were injected into the main sub-modules within the object-tracking...
With the increase in usage of low-power electronics in security critical area, demand for secure transmission of private and confidential information is on the rise. Implementation of dedicated hardware for cryptography is essential nowadays, even in the resource-constrained devices, to meet high-security concerns. However, hardware implementation of cryptographic algorithms may result in security...
This paper proposes novel soft error detection and mitigation technique in reduced instruction set computer (RISC) based pipeline processors. We leveraged the data encoding techniques (re-computing with rotated operands (RERO)) in conjunction with back pressure controlling mechanism in pipeline architecture. In order to alleviate the performance degradation due to potential stalling, we exploited...
This paper proposes a 1-1 MASH ΔΣ time-to-digital converter (TDC). A cascode time adder with a raised inverter threshold voltage is proposed to minimize the jitter caused by current mismatch. A differential time integrator consisting of two single-ended time integrators is proposed to minimize even-order harmonics. The detrimental effect of the nonidealities of the TDC is examined in detail. The TDC...
In this paper it will be shown that propagating specific state registers in a fully parallel Delta-Sigma Architecture can have a profound impact in enhancing the performance of these type of modulators without stringent requirements in terms of latency and resources usage. An FPGA-based transmitter was implemented and designed to validate the proposed architecture, and to demonstrate that flexible,...
This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
Approximate computing is gaining increasing interest among the VLSI design community due to its potential for enabling low power, high speed, and less area while delivering acceptably correct computation results for many digital signal processing applications. In this context, this paper considers for the first time asynchronous quasi-delay-insensitive (QDI) realizations of approximate adders which...
In this paper, a novel neural network architecture is proposed which results in an area-efficient feed-forward network. These structures require high-resolution multipliers. In order to overcome this problem, a mixed-signal Multiplying Digital to Analog Converter (MDAC) architecture which employs Delta-Sigma Modulation (DSM) to encode the multiplication results into the time domain. The time-domain...
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