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This brief presents the SoC-FPGA implementation of the modified Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm. The implementation was carried out by using hardware/software co-design based on software profiling that helped to find out that pseudo-random Spectral Permutation, Windowing, and Sub-Sampling (SPWS) are the signal processing operations that require most processing time in...
A 7GS/s 6b sub-ranging ADC is implemented in 32nm CMOS SOI with reconfigurable comparators, and adjustable input differential pairs are exploited to change converter characteristics for hardware-based cybersecurity. To achieve low-power consumption at high-speed operation with small-size transistors, an on-chip calibration to reduce process mismatches is utilized in the design. The presented ADC achieves...
This work addresses the problem of estimating the accuracy of a certain class of digital signal processing algorithms, known as linear signal transforms, when implemented on field programmable gate array (FPGA) hardware computational structure (HCS) units. A solution is provided through the formulation of a hardware development framework which uses complex multipliers and complex addition units as...
The need for large primes in major cryptographic algorithms has stirred interest in methods for prime generation. Recently, to improve confidence and security, prime number generation in hardware is being considered as an alternative to software. Due to time complexity and hardware implementation issues, probabilistic primality tests are generally preferred. The Baillie-PSW primality test is a strong...
In a world where electronics is becoming increasingly ubiquitous, the challenge of powering devices is progressively becoming more difficult. Often it is impractical to replace batteries or line power numerous devices. Energy harvesting is an attractive alternative but has the inherent disadvantage of frequent power loss. For processing systems like microcontrollers (MCUs) power restoration usually...
In this paper, we propose a cross-layer integrated microprocessor design methodology where instructions in software programs drive the design down to the gate level netlists. Based on in-depth exploration of the dynamic timing behavior of each instruction in the program, a fully integrated design approach is proposed with ultra-dynamic clock and power management circuits and software driven design...
Due to economies of scale and advancement in silicon technologies, powerful computing platforms are ushering a new era in computing and connectivity. These platforms are sometimes categorized under the umbrella of Internet of Things (IoT). In this paper, one such platform is used to design and build an Internet of Things solar tracker. The solar tracker predicts the sun position for maximum power...
Significant recent research activities and initiatives by local governments to establish resilient smart city infrastructures signal that time is right for smart cities in the near future. For example, sensors deployed within a city could monitor traffic patterns, perform environmental measurements and determine optimum traffic routing, when deployed in areas that have a power infrastructure. In this...
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