The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
Outsourcing designs to 3rd party vendors is a common practice in the integrated circuit (IC) manufacturing industry. This outsourcing brings advantages such as lower manufacturing cost and shorter time-to-market for a new system, which at the same time raises security threats in the IPs from 3rd party vendors. These IPs may contain hardware Trojans capable of compromising the product's confidentiality,...
A general methodology of device array mismatch characterization is introduced, analyzed and verified. Instead of measuring each device's parameter individually, the device array is configured as a data converter and the mismatch information is extracted from the differential linearity (DNL) of the converter. Systematic and random mismatch are characterized separately using the proposed decomposition...
In this paper, an advanced layout scheme of an integrated capacitor is presented which improves the efficiency of a poly-poly capacitor based voltage doubler charge pump. The main losses in voltage doubler charge pumps are mathematically described and the importance of low stray capacitances are discussed. By means of the improved poly-poly capacitor layout, the usable capacitance is increased while...
In this paper, we present artificial neural network (ANN) models to predict hard and soft-responses of three configurations of arbiter based physical unclonable functions (PUFs): standard, feed-forward (FF) and modified feed-forward (MFF). The models are trained using data extracted from 32-stage arbiter PUF circuits fabricated using IBM 32 nm HKMG process. The contributions of this paper are two-fold...
Spin based memories have garnered major interest in recent times. With all of the alluring features like-non-volatility, zero-stand by leakage and dense integration in array, they suffer from not having satisfactory distinguishability between stored memory states. Recently, a novel approach of using Phase transition materials (PTM) to assist magnetic tunnel junction (MTJ) in spin memories has been...
This work presents a 180-nm CMOS bandpass ΣΔ Analog-to-Digital Converter (ADC) developed to fulfill the specifications of a fully-integrated receiver for Magnetic Resonance Imaging (MRI). CMOS integration of a multichannel digital receiver would increase the quality of the image without the need of using many coaxial cables to connect the RF coils (located close to the patient) with the digitizing...
The standard LSTM recurrent neural networks while very powerful in long-range dependency sequence applications have highly complex structure and relatively large (adaptive) parameters. In this work, we present empirical comparison between the standard LSTM recurrent neural network architecture and three new parameter-reduced variants obtained by eliminating combinations of the input signal, bias,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.