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This paper introduces a multi-loop fast transient response flipped voltage follower (FVF) low-dropout (LDO) voltage regulator suitable for system-on-chip (SOC) applications. While typical FVF-based LDOs exhibit fast transient response, which is critical for SOC applications, their output DC accuracy is limited due to low loop gain of the FVF. In this work, we introduce a multi-loop design aimed at...
This paper presents a monolithically implemented NFC bicycle tire pressure measurement system (BTPMS) with integrated antenna, on-chip capacitive pressure and temperature sensor, RFID interface for HF/NFC and EEPROM. This NFC BTPMS has been designed using a 130 nm standard CMOS process and has an active chip area of 5.76 mm2. It provides significant cost advantages and impresses with its large scale...
The expanding use of deep learning algorithms causes the demands for accelerating neural network (NN) signal processing. For the NN processing, in-memory computation is desired, in which expensive data transfer can be eliminated. In reflection of recently proposed binary neural networks (BNNs), which can reduce the computation resource and area requirements, we designed an in-memory BNN signal processor...
Distributed on-chip low dropout (LDO) voltage regulators have become common due to the increasing number of on-chip voltage domains, dynamic voltage scaling, and the need for high quality power. Due to the current limitations of on-chip LDOs, hundreds of these regulators are required to deliver high quality power within modern high performance microprocessors. As the number of parallel connected LDOs...
In this study, CMOS-based on-chip neural interface devices with integrated optical stimulation capability are presented. The devices are designed for use in optogenetic applications. Two types of neural stimulators are presented. In one type, the on-chip CMOS image sensor was integrated with blue LEDs. Variations of device structures were developed as well. An in vivo experimental demonstration using...
This paper explores the use of On-chip cryptographic units for implementing security in low cost wireless sensor networks. The objective of this research is to reduce the deployment time and computational complexity of security protocols in WSNs, whilst keeping security related performance parameters at par with the current state-of-the-art. A method is proposed to continue using simple radio transreceiver...
An ultra-low power autonomous MPPT algorithm that maximizes the efficiency of a monolithic 0.98 mm2 solar harvester is presented. Using only the pn-junctions of the standard 130 nm single n-well process, the monolithic harvester can serve as supply for wireless sensor grains. Based on the perturbation and observation method, the MPPT algorithm maximizes the output current of the integrated charge...
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