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In this paper, we propose an adaptive routing algorithm for vertically partially connected 3D NoCs to (1) overcome failures in vertical links, and (2) find the nearest available vertical link for rerouting of packets. To track the position of each vertical link and distance to the other nodes, the proposed routing algorithm, named Advertiser Elevator, indexes each vertical link and implements a mechanism...
This paper proposes implementing an antenna operating in the millimeter wave band of 56–64 GHz on the backside of an Integrated Circuit (IC) that uses Through Silicon Via (TSV) technology for a System in Package (SiP) approach to mixed signal design. A folded monopole antenna that utilizes a coaxial TSV feed line is selected to implement the design on the backside of the silicon die. Furthermore,...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
A novel 2-Terminal, 3-Cell, Mechanical-Stack (2T3CMS) is designed and simulated in Silvaco Atlas to overcome instrinsic limitations of state-of-the-art designs. Indium-Gallium-Phosphide, Gallium-Arsenide and Germanium back-contact solar cells are current-matched and connected in series to achieve 32.5% and 29.2% power conversion efficiency at AM1.5G and AM0 (300 K), respectively. Two-terminal operation...
Enhancing energy/resource efficiency of neural networks is critical to support on-chip neural image processing at Internet-of-Things edge devices. This paper presents recent technology advancements towards energy-efficient neural image processing. 3D integration of image sensor and neural network improves power-efficiency with programmability and scalability. Computation energy of feedforward and...
3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology...
We present a mobile vehicle classification technique achieved by tracking two vehicle based Points of Interest (PoI) in multiple filter configurations to compose a vehicle specific 3D geometry. Using high fidelity physics based simulation we demonstrate the capability to classify the 3D geometries in the presence of noise by extracting vector magnitudes and angles as features. Additionally, we investigate...
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