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Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel...
In this paper, an low power CMOS temperature sensor for implantable applications is implemented in a 0.18 μm CMOS process. Sensors for implantable devices must have sub-μW power consumption to avoid tissue overheating. Thus, this temperature sensor employs subthreshold MOS transistors as the sensing element to reduce power consumption and enable minimum supply voltage. Temperature is converted to...
In this paper we present circuit techniques to optimize analog neurons specifically for operation in memristive neuromorphic systems. Since the peripheral circuits and control signals of the system are digital in nature, we take a mixed-signal circuit design approach to leverage analog computation in multiplying and accumulating digital input spikes and generate binary spikes as outputs to be consistent...
This paper proposes a highly sensitive RF-to-DC power converter with an extended dynamic range that is designed to operate at the medical band 433 MHz and simulated using 0.18 μm CMOS technology. Compared to the conventional fully cross-coupled rectifier, the proposed design offers 3.2× the dynamic range. It is also highly sensitive and requires −18 dBm of input power to produce a 1 V-output voltage...
This paper presents an adaptive edge decision feedback equalizer (DFE) with 4PAM signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are obtained adaptively using sign-sign least-mean-square (SS-LMS) algorithms that minimize data jitter. Clock and data recovery is carried out using a dual phase/frequency-locked loop. A 10 Gbps 4PAM serial link has been designed in a 65...
The paper describes evaluation of the first, second and (with most attention to) third harmonics of the drain current in a MOS transistor operating in moderate inversion. The dependence of this current on the gate-source voltage is approximated using a simplified “reconciliation” model developed by Y. Tsividis. Then, the drain current components depending exponentially on normalized signal voltage...
In this paper, for the first time, it is demonstrated that the start-up value of an SRAM PUF could be different depending on the SRAM power supply rising time. An analytical model has been developed to determine the range for the power supply ramp time that affects the SRAM PUF start-up value. It has been found that there are two regions of operation. As a result, the generated key could possibly...
Spiking Neural Networks offer low precision communication, robustness, and low power consumption and are attractive for autonomous applications. One of the well accepted learning rules for these networks is spike time dependent plasticity which is governed by the pre- and postsynaptic spike timings. To stabilize the plasticity and avoid saturation in these learning rules, synaptic normalization is...
Interfacing techniques for near-threshold computing are described in this paper. A bi-directional input/output circuit with integrated level shifters is proposed for multiple near-threshold power domains. The circuit provides conversion ranges of 0.38 V to 1.2 V and 0.45 V to 3.3 V depending on the targeted output voltage. Eight different configurations of I/O circuits are evaluated with level shifters...
Associate and approximate computing using resistive memory based Ternary Content Addressable Memory is becoming widely used. In this paper, a simplified model based analysis of a 2T2M-Ternary Content Addressable Memory using memristors is introduced. A comprehensive study is presented taking into consideration different circuit parameters and parasitic effects. Parameters such as the memristor Rh/R...
This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only...
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