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Spiking Neural Networks (SNNs) are the third generation of artificial neural networks that closely mimic the time encoding and information processing aspects of the human brain. It has been postulated that these networks are more efficient for realizing cognitive computing systems compared to second generation networks that are widely used in machine learning algorithms today. In this paper, we review...
We present the design and implementation of a monolithic microwatt analog front end and asynchronous level-crossing ADC for efficient capture of sparse biopotentials. The low-noise differential AC-coupled front-end provides +40 dB gain, and the signal is digitized by an asynchronous level-crossing ADC which encodes the signal slope into a stream of pulses. For temporally-sparse signals such as single-unit...
Timing leakage can be exploited to break a cryptographic system. Even though timing attacks have been well-researched for the past decade, recent system implementations remain highly vulnerable to these attacks. There is a critical need to develop a framework for automatic evaluation of vulnerability of a design against these attacks, so that integrated circuit designers can understand the vulnerability...
With the increase in usage of low-power electronics in security critical area, demand for secure transmission of private and confidential information is on the rise. Implementation of dedicated hardware for cryptography is essential nowadays, even in the resource-constrained devices, to meet high-security concerns. However, hardware implementation of cryptographic algorithms may result in security...
An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing...
Locally NOR and globally NAND match-line architecture and sensing circuits applicable to the high performance content addressable memory(CAM) is proposed in this paper. As word-length of CAM gets longer, the capacitance of match-line gets larger and it causes performance degradation and large dynamic power consumption. Local match-lines are segments of large capacitive match-line and designed as NOR-type...
Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. In this work, we propose a new cache architecture, called Janus, to enable crypto-systems to introduce randomization and uncertainty in their runtime timing behavior...
An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step...
Spiking Neural Networks offer low precision communication, robustness, and low power consumption and are attractive for autonomous applications. One of the well accepted learning rules for these networks is spike time dependent plasticity which is governed by the pre- and postsynaptic spike timings. To stabilize the plasticity and avoid saturation in these learning rules, synaptic normalization is...
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