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The flipped voltage follower (FVF), a variant of the common-drain transistor amplifier, comprising local feedback, finds application in circuits such as voltage buffers, current mirrors, class AB amplifiers, frequency compensation circuits and low dropout voltage regulators (LDOs). One of the most important characteristics of the FVF, is its low output impedance. In this tutorial-flavored paper, we...
This paper presents a method for calculating the semiconductor losses in asynchronous and synchronous PWM buck converters when operated as a fixed-VI, fixed-RL, variable-Vo dynamic power supply. Equations are derived for MOSFET switching and conduction losses in both circuits, as well as diode conduction and forward-voltage losses. This work also compares the two topologies from the perspective of...
This paper focuses on the design and analysis of multi-stage noise-shaping (MASH) sigma-delta modulators. Fundamentals and properties of MASH modulators are discussed. A detailed methodology on analyzing continuous-time MASH (CT-MASH) modulator based on the impulse invariant transformation is also described. Two fabricated design examples are discussed: a 130 nm CMOS CT-MASH 4-0 employing a digital...
Intravascular ultrasonic (IVUS) imaging catheters currently use ceramic piezoelectric transducers to form radial images of blood vessel walls. Further improvements in image quality may be enabled through Capacitive and Piezoelectric Micromachined Ultrasonic Transducers (CMUTs and PMUTs). Polymer PMUTs offer many benefits in imaging quality, however, the low acoustic sensitivity and high electrical...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
Exploiting resource reusability and low precision in neural networks is a promising approach to achieve energy efficient computational platforms. This research presents two generalizable approaches to reuse resources in feed-forward neural networks and demonstrated on extreme learning machines. In the first approach, coalescing, a single stack of neuronal units perform both feature extraction and...
In this paper, an electronically tunable immitance circuit is proposed. The presented circuit can be configured as a tunable grounded inductor or capacitor multiplier. The proposed circuit employs a single active element called Voltage Differential Current Conveyor, a single resistor and a single capacitor. The presented circuit does not require element matching constraints. It is linearly tunable...
An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step...
This paper compares the energy consumption used for communication in the special case of a wireless sensor network that is deployed linearly over a long distance to monitor assets such as transmission lines or pipelines. A model for energy consumption is developed based on a suitable network architecture for a linear wireless sensor network (WSN). Using the model, the energy consumption of networks...
3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology...
Interfacing techniques for near-threshold computing are described in this paper. A bi-directional input/output circuit with integrated level shifters is proposed for multiple near-threshold power domains. The circuit provides conversion ranges of 0.38 V to 1.2 V and 0.45 V to 3.3 V depending on the targeted output voltage. Eight different configurations of I/O circuits are evaluated with level shifters...
Two Band-Pass (BP) Discrete Time (DT) ΔΣ modulators are proposed in this paper. In both cases, the drawback of high-speed power-hungry adder is tackled by proposing a modified unity signal transfer function (STF) adder-less feedforward structure. The first proposed BP DT ΔΣ modulator is a conventional adder-less multi-stage noise shaping (MASH) ΔΣ modulator, while the noise leakage problem, caused...
This paper presents an overview of the design considerations and challenges of event-driven wakeup receivers as well as an analysis of state-of-the-art (SOA) research. We consider advantages and disadvantages of the commonly utilized architectures in these systems as well as presenting big picture perspectives from an application standpoint. This paper focuses on event-driven scenarios where the activity...
Electricity grid complexity with its diverse critical infrastructures has been continuously evolved into a more complicated network that is vulnerable to unpredictable hazards of internal and external origins. Resiliency assessment of the large-scale smart electricity grids has recently attracted many attentions in electric industry for more efficient daily operations in face of emergencies. This...
A 40V tolerant current limited voltage source for a wide input current range is presented. Integrated current limited voltage sources are needed for diagnosis purposes in automotive applications like airbag squib drivers that deploy airbags. The topology proposed here overcomes the conventional on chip Zener based topology that is sensitive to process variations and provides reliable operation in...
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