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As a popular deep learning technique, convolutional neural network has been widely used in many tasks such as image classification and object recognition. Convolutional neural network exploits spatial correlations in the images by performing convolution operations in local receptive fields. Convolutional neural networks are preferred over fully connected neural networks because they have fewer weights...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
We present a hardware-friendly spatiotemporal compressed sensing framework for video compression. The spatiotemporal compressed sensing incorporates random sampling in both spatial and temporal domain to encode the video scene into a single coded image. During decoding, the video is reconstructed using dictionary learning and sparse recovery. The evaluation results demonstrate the proposed approach...
Although microsensors nowadays can save money, energy, and lives, highly functional devices can exhaust a tiny battery very quickly. Harvesting ambient energy can help replenish the battery, but only when an ambient source is available. Unfortunately, many embedded microsensors are small, stationary, and enclosed, so thermal gradients, motion, and light are absent. Wireless power in these cases is...
This paper focuses on the design and analysis of multi-stage noise-shaping (MASH) sigma-delta modulators. Fundamentals and properties of MASH modulators are discussed. A detailed methodology on analyzing continuous-time MASH (CT-MASH) modulator based on the impulse invariant transformation is also described. Two fabricated design examples are discussed: a 130 nm CMOS CT-MASH 4-0 employing a digital...
A novel multi-dimensional noise-shaping method is proposed to extend Δ-Σ modulation to the two-dimensional (2-D) (space, time) case. It uses spatial oversampling to provide another degree of freedom for ADC designers to shape quantization noise when temporal oversampling is limited. The method uses lossless discrete integrators (LDIs) to implement spatial integrators and is suitable for use in microwave...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
LDPC codes have been applied in recent communication standards, such as WiFi, WiGig, and 10GBased-T Ethernet as a forward error correction code. However, LDPC codes require a large number of computational complexity for high performances. To solve this problem, various studies have been continuously performed for reducing computational complexity. In this paper, we propose an adaptive forced convergence...
Wireless transceivers that receive data and power are important circuit blocks in implantable biomedical devices. In such wirelessly powered devices, supply and common-mode variations increase the error rate of the received data. In this paper we propose a fully-differential amplitude-shift-keying (ASK) demodulator for suppressing the effect of such undesired common mode variations on the received...
This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant...
This paper presents an overview of various challenges, optimization strategies, and design requirements for subthreshold SRAM arrays targeting Ultra-Low Power (ULP) applications in the Internet of Things (IoTs). We study the impact of threshold voltage (VT) change due to process and temperature variations on various SRAM design decisions for ULP operation. We explore different solutions to enable...
Compressive sensing (CS) is a recent signal processing paradigm that exploits the inherent sparsity in input signal through data compression before wireless transmission. Recent CS implementations have shown impressive energy-efficiencies with good signal recovery but require apriori sparsity estimation and are thus not adaptable dynamic IoT environments resulting in loss of accuracy. This paper describes...
For autonomous medium power (1–10 W) field systems deployed in off-grid applications without established power infrastructure, two system design criteria are crucially important: i) continuous availability of power, ii) robust and low-maintenance operation. In this paper, we provide circuit and system designs for energy harvesters that address both issues by utilizing supercapacitors as their energy...
A self-start and self-powered power management circuit for impact-type piezoelectric energy harvester for speed bump is proposed. The piezoelectric impact-type cantilever was used to harvest the energy from speed bump as it is suitable for converting the low-frequency mechanical impact to high-frequency vibrations. Considering that vehicles passing through the speed bump are intermittent and random,...
Sedimentary microbial fuel cells are promising harvesting systems generating powers as low as 10 μW, which is sufficient for powering underwater environmental sensors. This paper proposes a methodology and modeling to design a flyback converter in discontinuous conduction mode harvesting powers as low as 10th of μWs to maximize the harvested energy and boost its voltage to a minimum value required...
A new headphone driver IC based on a switching output stage in continuous conduction mode is described. The driver uses a sliding-mode peak-valley control scheme to regulate the inductor current. The output stage is switched between the battery voltage and the output of an integrated non-regulated inverting charge pump, and a second-order loop filter is used to regulate the output voltage. The system...
To meet the demands of modern mobile devices on higher current and longer standby time, a novel high driving capability multi-phase interleaved buck converter with low standby power consumption is proposed. By transferring the control scheme from adaptive-on-time (AOT) mode to pulse-frequency-modulation (PFM) mode, the efficiency at light load could be improved. Phases can automatically shed to minimize...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
In this paper, a Reference Injected Phase-Locked Loop (PLL-RI) with delay-line ring-type oscillator is employed to implement a low-noise, fast locking integer-N frequency synthesizer. This inductor-less PLL-RI is fabricated in a 1.2V, 130nm RF CMOS process with a 0.5–1.7GHz tracking range in a 0.02 mm2 core area. Simulation and measurement results show phase noise reduction and improved settling behavior...
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