The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper we present circuit techniques to optimize analog neurons specifically for operation in memristive neuromorphic systems. Since the peripheral circuits and control signals of the system are digital in nature, we take a mixed-signal circuit design approach to leverage analog computation in multiplying and accumulating digital input spikes and generate binary spikes as outputs to be consistent...
Buffer-driven TSVs (BD-TSV) are widely used in 3D on-chip memories, especially in bit-line circuit that is highly sensitive to delay time. Closed form delay models for BD-TSVs are proposed in this paper and are verified by simulation through a 128 KB 3D on-chip memory in both 180 nm and 16 nm technology. Results show that the error rate of models is less than 8.9%, which can be accepted in design...
The ever-increasing need for higher number of neural recording channels along with the stringent power and area requirements of a brain-implantable device, demand for ultra-compact and scalable channel architectures. In this paper, we will first briefly discuss the fundamental scaling issues of conventional AC- and DC-coupled neural front-ends. Next, we will analytically examine the feasibility of...
Intravascular ultrasonic (IVUS) imaging catheters currently use ceramic piezoelectric transducers to form radial images of blood vessel walls. Further improvements in image quality may be enabled through Capacitive and Piezoelectric Micromachined Ultrasonic Transducers (CMUTs and PMUTs). Polymer PMUTs offer many benefits in imaging quality, however, the low acoustic sensitivity and high electrical...
In this study, CMOS-based on-chip neural interface devices with integrated optical stimulation capability are presented. The devices are designed for use in optogenetic applications. Two types of neural stimulators are presented. In one type, the on-chip CMOS image sensor was integrated with blue LEDs. Variations of device structures were developed as well. An in vivo experimental demonstration using...
This paper presents a wirelessly-powered and free-floating implantable optogenetic stimulating (FF-WIOS) implant with negligible footprint and high power transfer efficiency (PTE). FF-WIOS ASIC with embedded μLED and reflective lens is expected to stimulate the target cortical neuronal ensembles at high temporal and spatial resolution with minimal damage and no tethering effects. To improve the PTE,...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
The growing architectural complexity of Unified Extensible Firmware Interface (UEFI) requires a functional validation during system testing which in turn is becoming more complex and time-consuming. Unfortunately, there are few available solutions specifically designed to address this issue. We have proposed a novel technique which can automatically generate Colored Petri Net (CPN) from the UEFI firmware...
Hardware implementations of Object-Tracking Algorithms, like most integrated circuits, are susceptible to radiation-induced soft errors. This work evaluated the reliability of a field-programmable gate array (FPGA) prototype for object-tracking algorithms via fault emulation experiments conducted at the register-transfer level (RTL). Faults were injected into the main sub-modules within the object-tracking...
This paper presents a two-stage comb decimation filter for odd decimation factors, which are factors of three. The first stage is a comb decimated by M/3, (M is the overall decimation factor), while the second stage is a comb, decimated by three. The aliasing rejection is improved by cascading a simple multiplierless filter in the second stage. As a consequence, the aliasing rejection is improved...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced....
For a growing pool of data-intensive applications, data transfer, rather than processing speed, has emerged as the major bottleneck to performance and energy scalability. In this paper, we propose a novel interleaved logic-in-memory architecture, referred to as MISK, which leverages fine-grained integration of logic functions within dense, 2-D static random-access memory (SRAM) arrays for in-situ...
A recently proposed novel nanomagnetic co-processor harnesses the quadratic Hamiltonian of a system of coupled nanomagnets in order to solve quadratic optimization problems. The key principle here is “Let physics do the computation” in the sense that the relaxation physics of a grid of nanomagnets directly solve the optimization problem [1]. More interestingly, our preliminary research suggests that...
Ferroelectric RAM (FRAM) is a non-volatile memory with fast, low power, high endurance, read and write operations. Hence, this technology remains an attractive choice for embedded system solutions. In this paper, we analyze Si data that initiated the effort to design a compensated Sense Amplifier (SA) with improved input offset-sigma. We evaluate the cost vs benefit tradeoffs associated with this...
Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU...
Spiking Neural Networks (SNNs) are the third generation of artificial neural networks that closely mimic the time encoding and information processing aspects of the human brain. It has been postulated that these networks are more efficient for realizing cognitive computing systems compared to second generation networks that are widely used in machine learning algorithms today. In this paper, we review...
A spiking neuron and 3-terminal Resistive RAM (RRAM) model are proposed and simulated as a neural network. The system is analyzed as a complex network of spiking neurons connected by synapses to demonstrate a biologically-inspired associative memory. In recent years, Machine Learning and Artificial Intelligence have become popular fields due to readily available high performance computing systems...
This paper proposes a highly sensitive RF-to-DC power converter with an extended dynamic range that is designed to operate at the medical band 433 MHz and simulated using 0.18 μm CMOS technology. Compared to the conventional fully cross-coupled rectifier, the proposed design offers 3.2× the dynamic range. It is also highly sensitive and requires −18 dBm of input power to produce a 1 V-output voltage...
This paper proposes a lag-lead Active Voltage Positioning (AVP) technique that can be used in buck converters to minimize their output voltage transients during dynamic events, such as load pulses. The proposed technique is based on optimizing the output impedance of the converter across a wide range of frequencies, and therefore, output voltage transients in response to both narrow and wide load...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.