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Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
A serial-link repeater chip with a single stage continuous-time linear equalizer (CTLE) and a 3-tap feedforward equalizer (FFE) is realized in a 0.13μm SiGe BiCMOS technology. The CTLE with the negative capacitance circuits is implemented to achieve a larger high-frequency boosting at the receiver side. By utilizing the LC-based delay elements, the FFE accomplishes the transmitter de-emphasis without...
Conventional decision feedback equalizers (DFEs) suffer from the fundamental drawback of shrinking rather than increasing data eyes when consecutive 1s or 0s are present in data. To combat this drawback, a new data-transition adaptive DFE is proposed. The proposed DFE takes into account the dependence of post-cursors on the polarity of data and searches for optimal tap coefficients using a sign-sign...
This paper presents an adaptive edge decision feedback equalizer (DFE) with 4PAM signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are obtained adaptively using sign-sign least-mean-square (SS-LMS) algorithms that minimize data jitter. Clock and data recovery is carried out using a dual phase/frequency-locked loop. A 10 Gbps 4PAM serial link has been designed in a 65...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
Exploiting resource reusability and low precision in neural networks is a promising approach to achieve energy efficient computational platforms. This research presents two generalizable approaches to reuse resources in feed-forward neural networks and demonstrated on extreme learning machines. In the first approach, coalescing, a single stack of neuronal units perform both feature extraction and...
In this paper we present a memristive neuromorphic system for higher power and area efficiency. The system is based on a mixed signal approach considering the digital nature of the peripheral and control logics and the integration being analog. So, the system is connected digitally outside but the core is purely analog. This mixed signal approach provides the advantage of implementing neural networks...
A novel offset calibration technique with fast convergence rate for high-speed dynamic comparators is presented. The circuit utilizes a multi-rate charge pump circuitry to speed up the calibration process while maintaining the precision which leads to better energy efficiency. The circuit is designed in a 0.13μm CMOS process. Based on Monte-Carlo simulation results the comparator achieves 183.1μV...
In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation,...
Timing leakage can be exploited to break a cryptographic system. Even though timing attacks have been well-researched for the past decade, recent system implementations remain highly vulnerable to these attacks. There is a critical need to develop a framework for automatic evaluation of vulnerability of a design against these attacks, so that integrated circuit designers can understand the vulnerability...
Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware...
Outsourcing designs to 3rd party vendors is a common practice in the integrated circuit (IC) manufacturing industry. This outsourcing brings advantages such as lower manufacturing cost and shorter time-to-market for a new system, which at the same time raises security threats in the IPs from 3rd party vendors. These IPs may contain hardware Trojans capable of compromising the product's confidentiality,...
This paper provides a proof-of-concept demonstration of the potential benefit of using logical implications for detection of combinational hardware trojans. Using logic simulation, valid logic implications are selected and added to to the checker circuitry to detect payload delivery by a combinational hardware trojan. Using combinational circuits from the ISCAS benchmark suite, and a modest hardware...
With the increase in usage of low-power electronics in security critical area, demand for secure transmission of private and confidential information is on the rise. Implementation of dedicated hardware for cryptography is essential nowadays, even in the resource-constrained devices, to meet high-security concerns. However, hardware implementation of cryptographic algorithms may result in security...
This paper presents an overview of high speed ADCs for wireline applications. In the first part of the paper, the need for an ADC-based wireline link is justified, which is then followed by a discussion on the architecture of an ADC-based transceiver. We conclude this paper by discussing the challenges and trade-offs of designing high speed ADCs for wireline applications.
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to...
This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency...
An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing...
A general methodology of device array mismatch characterization is introduced, analyzed and verified. Instead of measuring each device's parameter individually, the device array is configured as a data converter and the mismatch information is extracted from the differential linearity (DNL) of the converter. Systematic and random mismatch are characterized separately using the proposed decomposition...
Genetic mutations are the first warning to the onset of lung cancer. The ability to early predict these mutations could open the door for a targeted treatment options for lung cancer patients. Three top candidate genes previously reported to have the highest frequency of lung cancer mutations. Each gene is encoded as a symbolic sequence of four letters. A novel method for gene representation is introduced...
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